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| author | Fernando Endo <fernando.endo2@gmail.com> | 2016-10-15 14:58:45 -0500 |
|---|---|---|
| committer | Fernando Endo <fernando.endo2@gmail.com> | 2016-10-15 14:58:45 -0500 |
| commit | 6c72c3551978ef2eabbe9727bf24fd2fcf385318 (patch) | |
| tree | d7b37cfe5b12e2136afe5f90ea22d67a512d0018 /src/cpu/minor | |
| parent | 2f5262eb67f0539ab6c07d56eeae1b72f6b6b509 (diff) | |
| download | gem5-6c72c3551978ef2eabbe9727bf24fd2fcf385318.tar.xz | |
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/minor')
| -rw-r--r-- | src/cpu/minor/MinorCPU.py | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py index 2c80af175..5954f7b1e 100644 --- a/src/cpu/minor/MinorCPU.py +++ b/src/cpu/minor/MinorCPU.py @@ -142,8 +142,8 @@ class MinorDefaultIntDivFU(MinorFU): class MinorDefaultFloatSimdFU(MinorFU): opClasses = minorMakeOpClassSet([ - 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', - 'FloatSqrt', + 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', + 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', @@ -154,7 +154,8 @@ class MinorDefaultFloatSimdFU(MinorFU): opLat = 6 class MinorDefaultMemFU(MinorFU): - opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite']) + opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', + 'FloatMemWrite']) timings = [MinorFUTiming(description='Mem', srcRegsRelativeLats=[1], extraAssumedLat=2)] opLat = 1 |