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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:09:02 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-03-14 10:42:27 +0000 |
| commit | c4cc3145cd1eeed236b5cd3f7b2424bc0761878e (patch) | |
| tree | b38eab6f5f389dfc53c2cf74275a83bacd2e9b18 /src/cpu/minor | |
| parent | 91195ae7f637d1d4879cc3bf0860147333846e75 (diff) | |
| download | gem5-c4cc3145cd1eeed236b5cd3f7b2424bc0761878e.tar.xz | |
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.
Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/minor')
| -rw-r--r-- | src/cpu/minor/MinorCPU.py | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py index ae97f6c4f..5aebbf805 100644 --- a/src/cpu/minor/MinorCPU.py +++ b/src/cpu/minor/MinorCPU.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2014,2018 ARM Limited +# Copyright (c) 2012-2014, 2017-2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -148,15 +148,24 @@ class MinorDefaultFloatSimdFU(MinorFU): 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', - 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', + 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', - 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix', + 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu', + 'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp', + 'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) + timings = [MinorFUTiming(description='FloatSimd', srcRegsRelativeLats=[2])] opLat = 6 +class MinorDefaultPredFU(MinorFU): + opClasses = minorMakeOpClassSet(['SimdPredAlu']) + timings = [MinorFUTiming(description="Pred", + srcRegsRelativeLats=[2])] + opLat = 3 + class MinorDefaultMemFU(MinorFU): opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite']) @@ -171,8 +180,8 @@ class MinorDefaultMiscFU(MinorFU): class MinorDefaultFUPool(MinorFUPool): funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), - MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), - MinorDefaultMiscFU()] + MinorDefaultFloatSimdFU(), MinorDefaultPredFU(), + MinorDefaultMemFU(), MinorDefaultMiscFU()] class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] |