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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
| commit | 005892719047c3b4b383d9aeeeb481039518f661 (patch) | |
| tree | b2d967a9ffea13f73e092804ae141d9520ff109c /src/cpu/o3/FUPool.py | |
| parent | 2a3cefe15115a094eadd74a659a2f919a83ac6a4 (diff) | |
| download | gem5-005892719047c3b4b383d9aeeeb481039518f661.tar.xz | |
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Diffstat (limited to 'src/cpu/o3/FUPool.py')
| -rw-r--r-- | src/cpu/o3/FUPool.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py index 4f07f9867..1d3afbc6b 100644 --- a/src/cpu/o3/FUPool.py +++ b/src/cpu/o3/FUPool.py @@ -37,4 +37,4 @@ class FUPool(SimObject): class DefaultFUPool(FUPool): FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - WritePort(), RdWrPort(), IprPort() ] + SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] |