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| author | Fernando Endo <fernando.endo2@gmail.com> | 2016-10-15 14:58:45 -0500 |
|---|---|---|
| committer | Fernando Endo <fernando.endo2@gmail.com> | 2016-10-15 14:58:45 -0500 |
| commit | 6c72c3551978ef2eabbe9727bf24fd2fcf385318 (patch) | |
| tree | d7b37cfe5b12e2136afe5f90ea22d67a512d0018 /src/cpu/o3/FuncUnitConfig.py | |
| parent | 2f5262eb67f0539ab6c07d56eeae1b72f6b6b509 (diff) | |
| download | gem5-6c72c3551978ef2eabbe9727bf24fd2fcf385318.tar.xz | |
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/FuncUnitConfig.py')
| -rw-r--r-- | src/cpu/o3/FuncUnitConfig.py | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index b8be400b5..f0c70f55a 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -68,6 +68,8 @@ class FP_ALU(FUDesc): class FP_MultDiv(FUDesc): opList = [ OpDesc(opClass='FloatMult', opLat=4), + OpDesc(opClass='FloatMultAcc', opLat=5), + OpDesc(opClass='FloatMisc', opLat=3), OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] count = 2 @@ -96,15 +98,18 @@ class SIMD_Unit(FUDesc): count = 4 class ReadPort(FUDesc): - opList = [ OpDesc(opClass='MemRead') ] + opList = [ OpDesc(opClass='MemRead'), + OpDesc(opClass='FloatMemRead') ] count = 0 class WritePort(FUDesc): - opList = [ OpDesc(opClass='MemWrite') ] + opList = [ OpDesc(opClass='MemWrite'), + OpDesc(opClass='FloatMemWrite') ] count = 0 class RdWrPort(FUDesc): - opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] + opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'), + OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')] count = 4 class IprPort(FUDesc): |