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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-29 22:35:22 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-29 22:35:22 -0500 |
commit | 43335495754abac71377bbd6df0c668b60b22822 (patch) | |
tree | 62ca271baac3fafb041bf24acaaeef14f6ab8e97 /src/cpu/o3/FuncUnitConfig.py | |
parent | 0dbd696aaef47205c1430b53841423c7d25455ed (diff) | |
download | gem5-43335495754abac71377bbd6df0c668b60b22822.tar.xz |
cpu: o3: replace issueLatency with bool pipelined
Currently, each op class has a parameter issueLat that denotes the cycles after
which another op of the same class can be issued. As of now, this latency can
either be one cycle (fully pipelined) or same as execution latency of the op
(not at all pipelined). The fact that issueLat is a parameter of type Cycles
makes one believe that it can be set to any value. To avoid the confusion, the
parameter is being renamed as 'pipelined' with type boolean. If set to true,
the op would execute in a fully pipelined fashion. Otherwise, it would execute
in an unpipelined fashion.
Diffstat (limited to 'src/cpu/o3/FuncUnitConfig.py')
-rw-r--r-- | src/cpu/o3/FuncUnitConfig.py | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index 0f5efb776..b8be400b5 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -49,7 +49,7 @@ class IntALU(FUDesc): class IntMultDiv(FUDesc): opList = [ OpDesc(opClass='IntMult', opLat=3), - OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] + OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ] # DIV and IDIV instructions in x86 are implemented using a loop which # issues division microops. The latency of these microops should really be @@ -57,7 +57,6 @@ class IntMultDiv(FUDesc): # of the quotient. if buildEnv['TARGET_ISA'] in ('x86'): opList[1].opLat=1 - opList[1].issueLat=1 count=2 @@ -69,8 +68,8 @@ class FP_ALU(FUDesc): class FP_MultDiv(FUDesc): opList = [ OpDesc(opClass='FloatMult', opLat=4), - OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), - OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] + OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), + OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] count = 2 class SIMD_Unit(FUDesc): @@ -109,6 +108,6 @@ class RdWrPort(FUDesc): count = 4 class IprPort(FUDesc): - opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] + opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] count = 1 |