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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-28 19:09:04 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-28 19:09:04 -0600 |
| commit | 5c2fc35e029d8cd8e69e983e1baef6b86e47d64d (patch) | |
| tree | 03e3f37b4cef15a165f79b5dde0a7abee14e0523 /src/cpu/o3/O3CPU.py | |
| parent | 4acca8a0536d4445ed25b67edf571ae460446ab9 (diff) | |
| download | gem5-5c2fc35e029d8cd8e69e983e1baef6b86e47d64d.tar.xz | |
O3 CPU LSQ: Implement TSO
This patch makes O3's LSQ maintain total order between stores. Essentially
only the store at the head of the store buffer is allowed to be in flight.
Only after that store completes, the next store is issued to the memory
system. By default, the x86 architecture will have TSO.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 9dfcc8b9e..6f721a11b 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -143,3 +143,5 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") + needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', + "Enable TSO Memory model") |