diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
| commit | ec936364b7238cddea7734ea79c6e04b52a683c6 (patch) | |
| tree | 788fc19c3ba599d6f39d3990769888a0650be5ff /src/cpu/o3/O3CPU.py | |
| parent | 36a822f08e88483b41af214ace4fd3dccf3aa8cb (diff) | |
| parent | 9b52717a92ed9592bd98a41683509f538262a5c7 (diff) | |
| download | gem5-ec936364b7238cddea7734ea79c6e04b52a683c6.tar.xz | |
Merge with the main repository again.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 51643c169..1d8950a73 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -142,7 +142,3 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) - self.icache.tgts_per_mshr = 20 - self.dcache.tgts_per_mshr = 20 |