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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-20 19:04:37 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-20 19:04:37 +0000 |
| commit | 0a971cc0c9a6302afb6da5d561b7df24f443eca4 (patch) | |
| tree | 4a56e8a6ee996bdf2381be4cbaf5f7c540d3af8e /src/cpu/o3/O3CPU.py | |
| parent | a68ddf685c739220d09fdc44000dd217d0707f8e (diff) | |
| parent | 4a7bc06553577f25e8dc895fa20506c62455a4b6 (diff) | |
| download | gem5-0a971cc0c9a6302afb6da5d561b7df24f443eca4.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : f2fac2b1a09e709021cd8382a9fbe805df2177ef
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index e031faefa..e691cfe5d 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU): checker.itb = Parent.itb checker.dtb = Parent.dtb - cachePorts = Param.Unsigned("Cache Ports") + cachePorts = Param.Unsigned(200, "Cache Ports") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") _mem_ports = ['icache_port', 'dcache_port'] @@ -137,15 +137,15 @@ class DerivO3CPU(BaseCPU): function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") - smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") - smtFetchPolicy = Param.String("SMT Fetch policy") - smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") - smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") - smtIQPolicy = Param.String("SMT IQ Sharing Policy") - smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") - smtROBPolicy = Param.String("SMT ROB Sharing Policy") - smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") - smtCommitPolicy = Param.String("SMT Commit Policy") + smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") + smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") + smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") + smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") + smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") + smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") def addPrivateSplitL1Caches(self, ic, dc): BaseCPU.addPrivateSplitL1Caches(self, ic, dc) |