diff options
| author | Anthony Gutierrez <atgutier@umich.edu> | 2012-07-27 16:08:04 -0400 |
|---|---|---|
| committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-07-27 16:08:04 -0400 |
| commit | 8133f2460fa8a6201deb361989a1179a163140fb (patch) | |
| tree | 2fdfac8bad488bd9172f1450eca8084a1dcc0b3c /src/cpu/o3/O3CPU.py | |
| parent | 7bf14aedbf0a3b41e8a94701c582baf0d67a66fa (diff) | |
| download | gem5-8133f2460fa8a6201deb361989a1179a163140fb.tar.xz | |
checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading the
cpu id register failed because the ids did not match, and hence, the result
of the instruction did not match. this patch ensures that the ids match so
this instruction does not fail. this problem only seemed to manifest itself
when multiple cores were in the system, either multi-core, or extra switched-
out cores present in the system.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 042c5e637..3138aebbf 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -141,6 +141,7 @@ class DerivO3CPU(BaseCPU): warnOnlyOnLoadError=True) self.checker.itb = ArmTLB(size = self.itb.size) self.checker.dtb = ArmTLB(size = self.dtb.size) + self.checker.cpu_id = self.cpu_id else: print "ERROR: Checker only supported under ARM ISA!" |