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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/o3/O3CPU.py | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index d2220de82..92f96a3b6 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -114,7 +114,6 @@ class DerivO3CPU(BaseCPU): numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " "registers") - # most ISAs don't use condition-code regs, so default is 0 _defaultNumPhysCCRegs = 0 if buildEnv['TARGET_ISA'] in ('arm','x86'): @@ -127,12 +126,6 @@ class DerivO3CPU(BaseCPU): _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, "Number of physical cc registers") - - # most ISAs don't use vector regs, so default is 0 - _defaultNumPhysVectorRegs = 0 - numPhysVectorRegs = Param.Unsigned(_defaultNumPhysVectorRegs, - "Number of physical vector registers") - numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") |