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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:01 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:01 -0800 |
| commit | c3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch) | |
| tree | 5324ebec3add54b934a841eee901983ac3463a7f /src/cpu/o3/O3CPU.py | |
| parent | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff) | |
| parent | 4acca8a0536d4445ed25b67edf571ae460446ab9 (diff) | |
| download | gem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz | |
Merge with the main repo.
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 1d8950a73..ffc817e81 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -49,9 +49,6 @@ class DerivO3CPU(BaseCPU): checker.dtb = Parent.dtb cachePorts = Param.Unsigned(200, "Cache Ports") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port'] decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") |