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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
| commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
| tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/cpu/o3/O3CPU.py | |
| parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
| download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz | |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 4d215328e..1b25b2e7b 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -116,7 +116,7 @@ class DerivO3CPU(BaseCPU): "registers") # most ISAs don't use condition-code regs, so default is 0 _defaultNumPhysCCRegs = 0 - if buildEnv['TARGET_ISA'] == 'x86': + if buildEnv['TARGET_ISA'] in ('arm','x86'): # For x86, each CC reg is used to hold only a subset of the # flags, so we need 4-5 times the number of CC regs as # physical integer regs to be sure we don't run out. In |