diff options
| author | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-12-01 00:15:22 -0800 |
|---|---|---|
| committer | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-12-01 00:15:22 -0800 |
| commit | 61c14da751ae80e8c19e0b63ddd629c4152f1c72 (patch) | |
| tree | a1c74b7afe115082c4ca5a5f1797d3de14772041 /src/cpu/o3/O3CPU.py | |
| parent | fa753c14549a768f0b8475e4e183acbdc394c248 (diff) | |
| download | gem5-61c14da751ae80e8c19e0b63ddd629c4152f1c72.tar.xz | |
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 47b18a3ec..2a5b6782f 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -146,7 +146,3 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) - self.icache.tgts_per_mshr = 20 - self.dcache.tgts_per_mshr = 20 |