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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 08:37:30 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 08:37:30 -0600 |
| commit | cd765c23a2030d45223952315b4e862999714890 (patch) | |
| tree | 0bddf25b5ff70e31dd2fea912d65abe14e5dbfc1 /src/cpu/o3/O3CPU.py | |
| parent | 8f7e03d4cf4810fa3e09b134c2cf5b6df78a39b0 (diff) | |
| download | gem5-cd765c23a2030d45223952315b4e862999714890.tar.xz | |
O3 CPU: Strengthen condition for handling interrupts
The condition for handling interrupts is to check whether or not the cpu's
instruction list is empty. As observed, this can lead to cases in which even
though the instruction list is empty, interrupts are handled when they should
not be. The condition is being strengthened so that interrupts get handled only
when the last committed microop did not had IsDelayedCommit set.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
0 files changed, 0 insertions, 0 deletions