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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
| commit | b3f930c884ef23e4d784553fdccc91a772334fd7 (patch) | |
| tree | cafe3076cb93173cb0587e7f6c718efa178463e6 /src/cpu/o3/O3CPU.py | |
| parent | f85286b3debf4a4a94d3b959e5bb880be81bd692 (diff) | |
| download | gem5-b3f930c884ef23e4d784553fdccc91a772334fd7.tar.xz | |
CPU: Moving towards a more general port across CPU models
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 2a5b6782f..9dfcc8b9e 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -53,9 +53,6 @@ class DerivO3CPU(BaseCPU): checker.dtb = Parent.dtb cachePorts = Param.Unsigned(200, "Cache Ports") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port'] decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") |