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| author | Arthur Perais <arthur.perais@inria.fr> | 2016-12-21 15:04:06 -0600 |
|---|---|---|
| committer | Arthur Perais <arthur.perais@inria.fr> | 2016-12-21 15:04:06 -0600 |
| commit | e5fb6752d613a6f85e2f93b4c01836ac59a8c90c (patch) | |
| tree | 7bec60d7645ed4a1d7e20dc8071c0dafd288b786 /src/cpu/o3/O3CPU.py | |
| parent | 3a656da1a64f08d5e4c755e94cefda5a4e985a50 (diff) | |
| download | gem5-e5fb6752d613a6f85e2f93b4c01836ac59a8c90c.tar.xz | |
cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3
cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 92f96a3b6..cab2cf34f 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -52,7 +52,8 @@ class DerivO3CPU(BaseCPU): activity = Param.Unsigned(0, "Initial count") - cachePorts = Param.Unsigned(200, "Cache Ports") + cacheStorePorts = Param.Unsigned(200, "Cache Ports. " + "Constrains stores only. Loads are constrained by load FUs.") decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") |