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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
commiteb703a4b4e167e4d45f92203a1e0849f19cdba6d (patch)
tree390ab4209a18921923aa1e51c3f93398db74f3ef /src/cpu/o3/O3CPU.py
parentebe65a394bdb6b23d99fa01bcea105065a648991 (diff)
downloadgem5-eb703a4b4e167e4d45f92203a1e0849f19cdba6d.tar.xz
cpu: O3 add a header declaring the DerivO3CPU
SWIG needs a complete declaration of all wrapped objects. This patch adds a header file with the DerivO3CPU class and includes it in the SWIG interface. --HG-- rename : src/cpu/o3/cpu_builder.cc => src/cpu/o3/deriv.cc
Diffstat (limited to 'src/cpu/o3/O3CPU.py')
-rw-r--r--src/cpu/o3/O3CPU.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 6923e7b25..5fec3c547 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -35,6 +35,8 @@ from O3Checker import O3Checker
class DerivO3CPU(BaseCPU):
type = 'DerivO3CPU'
+ cxx_header = 'cpu/o3/deriv.hh'
+
activity = Param.Unsigned(0, "Initial count")
cachePorts = Param.Unsigned(200, "Cache Ports")