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authorKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
committerKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
commit6e969c31c7c0671ce201f40dd67afad2e9fee832 (patch)
tree1a7a5bc1e52dd54ff3319837fa87c018d8dd08b0 /src/cpu/o3/SConscript
parentf9729e999f71895f6b53f8189bdff535e7c7b70e (diff)
parent19ca97af79f3a40111991b4f8375592c7ede65fa (diff)
downloadgem5-6e969c31c7c0671ce201f40dd67afad2e9fee832.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
Diffstat (limited to 'src/cpu/o3/SConscript')
-rwxr-xr-xsrc/cpu/o3/SConscript15
1 files changed, 7 insertions, 8 deletions
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index e65d41411..44882e5ec 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -52,15 +52,14 @@ if env['TARGET_ISA'] == 'alpha':
alpha/cpu_builder.cc
''')
elif env['TARGET_ISA'] == 'mips':
- sys.exit('O3 CPU does not support MIPS')
- #sources += Split('''
- # mips/dyn_inst.cc
- # mips/cpu.cc
- # mips/thread_context.cc
- # mips/cpu_builder.cc
- # ''')
+ sources += Split('''
+ mips/dyn_inst.cc
+ mips/cpu.cc
+ mips/thread_context.cc
+ mips/cpu_builder.cc
+ ''')
elif env['TARGET_ISA'] == 'sparc':
- sys.exit('O3 CPU does not support MIPS')
+ sys.exit('O3 CPU does not support Sparc')
#sources += Split('''
# sparc/dyn_inst.cc
# sparc/cpu.cc