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authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:31 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:31 -0500
commit689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch)
tree2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/cpu/o3/alpha/cpu.hh
parent329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff)
downloadgem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/cpu/o3/alpha/cpu.hh')
-rw-r--r--src/cpu/o3/alpha/cpu.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 4a2086296..676893098 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl>
#endif
/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
- void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+ void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+ void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Initiates a squash of all in-flight instructions for a given