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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:44 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:44 -0500 |
commit | 49527ab55312bf02dfce20c45db8f173b0c2324e (patch) | |
tree | b9212b195a7b253940aaaab5c8b9ef27e43d026e /src/cpu/o3/alpha/cpu.hh | |
parent | ea7bdf9f60c404761dfc568d5291c75747a2dd88 (diff) | |
parent | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (diff) | |
download | gem5-49527ab55312bf02dfce20c45db8f173b0c2324e.tar.xz |
Merge zizzer:/bk/newmem
into zeep.pool:/tmp/newmem
--HG--
extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
Diffstat (limited to 'src/cpu/o3/alpha/cpu.hh')
-rw-r--r-- | src/cpu/o3/alpha/cpu.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 4a2086296..676893098 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl> #endif /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given |