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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:49:52 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:49:52 -0400 |
| commit | 74e80fc6c76d111a5c936c28ef739fd62fcebcaa (patch) | |
| tree | a8c555d4348b57e28e19dd075b493fed48265e0f /src/cpu/o3/alpha | |
| parent | cd6eb5396569bd2a3b16148f0d5277f7f4ee1391 (diff) | |
| download | gem5-74e80fc6c76d111a5c936c28ef739fd62fcebcaa.tar.xz | |
Some touchup to the reorganized includes and "using" directives.
--HG--
extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
Diffstat (limited to 'src/cpu/o3/alpha')
| -rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index c07595024..b7362fad9 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -31,6 +31,7 @@ #include "config/use_checker.hh" #include "arch/alpha/faults.hh" +#include "arch/alpha/isa_traits.hh" #include "base/cprintf.hh" #include "base/statistics.hh" #include "base/timebuf.hh" @@ -189,14 +190,14 @@ AlphaO3CPU<Impl>::regStats() template <class Impl> -MiscReg +TheISA::MiscReg AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) { return this->regFile.readMiscReg(misc_reg, tid); } template <class Impl> -MiscReg +TheISA::MiscReg AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid) { @@ -298,6 +299,7 @@ template <class Impl> void AlphaO3CPU<Impl>::processInterrupts() { + using namespace TheISA; // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 // is the one that handles the interrupts. @@ -409,12 +411,12 @@ AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - this->setArchIntReg(SyscallSuccessReg, 0, tid); - this->setArchIntReg(ReturnValueReg, return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid); + this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid); } else { // got an error, return details - this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid); - this->setArchIntReg(ReturnValueReg, -return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid); + this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid); } } #endif |