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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-05 16:08:18 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-05 16:08:18 -0400 |
| commit | b973fae85d47a8184204d5d38b32ad3d427ce41c (patch) | |
| tree | f101b7e4c91c1672bc21de12a4eb01e4120b1510 /src/cpu/o3/alpha | |
| parent | 4201ec84b2dd7d96148bf661124dd7b5d0e7204b (diff) | |
| parent | ae78c465313d6ca1dc71e8b9731e952bb3c8c09b (diff) | |
| download | gem5-b973fae85d47a8184204d5d38b32ad3d427ce41c.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
src/base/traceflags.py:
src/cpu/SConscript:
Hand merge.
src/cpu/o3/alpha/params.hh:
Hand merge. This needs to get changed.
--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
Diffstat (limited to 'src/cpu/o3/alpha')
| -rw-r--r-- | src/cpu/o3/alpha/cpu_builder.cc | 9 | ||||
| -rw-r--r-- | src/cpu/o3/alpha/params.hh | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index 490305cbf..d61eee4b1 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -91,7 +91,10 @@ Param<unsigned> renameWidth; Param<unsigned> commitToIEWDelay; Param<unsigned> renameToIEWDelay; Param<unsigned> issueToExecuteDelay; +Param<unsigned> dispatchWidth; Param<unsigned> issueWidth; +Param<unsigned> wbWidth; +Param<unsigned> wbDepth; SimObjectParam<FUPool *> fuPool; Param<unsigned> iewToCommitDelay; @@ -207,7 +210,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) "Issue/Execute/Writeback delay"), INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal" "to the IEW stage)"), + INIT_PARAM(dispatchWidth, "Dispatch width"), INIT_PARAM(issueWidth, "Issue width"), + INIT_PARAM(wbWidth, "Writeback width"), + INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"), INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL), INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit " @@ -333,7 +339,10 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->commitToIEWDelay = commitToIEWDelay; params->renameToIEWDelay = renameToIEWDelay; params->issueToExecuteDelay = issueToExecuteDelay; + params->dispatchWidth = dispatchWidth; params->issueWidth = issueWidth; + params->wbWidth = wbWidth; + params->wbDepth = wbDepth; params->fuPool = fuPool; params->iewToCommitDelay = iewToCommitDelay; diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh index b1f2a487d..8f7364dd0 100644 --- a/src/cpu/o3/alpha/params.hh +++ b/src/cpu/o3/alpha/params.hh @@ -64,6 +64,9 @@ class AlphaSimpleParams : public O3Params BaseCPU *checker; unsigned decodeToFetchDelay; + unsigned dispatchWidth; + unsigned wbWidth; + unsigned wbDepth; }; #endif // __CPU_O3_ALPHA_PARAMS_HH__ |