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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-26 22:13:14 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-26 22:13:14 -0700 |
| commit | d1e533a1e243b75b3257e2f96deb385a3b10e09b (patch) | |
| tree | 5cde70506a663c83efceced11273cca47fed9586 /src/cpu/o3/alpha | |
| parent | 876849724d0e5a990018dc025a8166c5131be567 (diff) | |
| download | gem5-d1e533a1e243b75b3257e2f96deb385a3b10e09b.tar.xz | |
X86: Fix argument register indexing.
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.
--HG--
extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
Diffstat (limited to 'src/cpu/o3/alpha')
| -rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 1754300d2..7f8f0547b 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -293,14 +293,16 @@ template <class Impl> TheISA::IntReg AlphaO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); } template <class Impl> void AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { - this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); } template <class Impl> |