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authorLisa Hsu <hsul@eecs.umich.edu>2007-01-26 12:51:07 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2007-01-26 12:51:07 -0500
commit202d7f62b9ea11e6b72c4b15ff818549ea14f038 (patch)
treef5f217121b907fe9cb78243dc35fcc12f17f596e /src/cpu/o3/alpha
parent01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1 (diff)
downloadgem5-202d7f62b9ea11e6b72c4b15ff818549ea14f038.tar.xz
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
Diffstat (limited to 'src/cpu/o3/alpha')
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 98fd0699a..980e70fdd 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid)
this->thread[tid]->kernelStats->hwrei();
- this->checkInterrupts = true;
-
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
@@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts.updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
- this->checkInterrupts = false;
this->trap(interrupt, 0);
}