Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.

First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a

1 files changed, 7 insertions, 7 deletions

diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index f81837f3c..4daa8b3ba 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -44,7 +44,7 @@ namespace Kernel {
 class TranslatingPort;
 
 /**
- * AlphaFullCPU class.  Derives from the FullO3CPU class, and
+ * AlphaO3CPU class.  Derives from the FullO3CPU class, and
  * implements all ISA and implementation specific functions of the
  * CPU.  This is the CPU class that is used for the SimObjects, and is
  * what is given to the DynInsts.  Most of its state exists in the
@@ -52,7 +52,7 @@ class TranslatingPort;
  * functionality.
  */
 template <class Impl>
-class AlphaFullCPU : public FullO3CPU<Impl>
+class AlphaO3CPU : public FullO3CPU<Impl>
 {
   protected:
     typedef TheISA::IntReg IntReg;
@@ -67,17 +67,17 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     typedef O3ThreadState<Impl> Thread;
     typedef typename Impl::Params Params;
 
-    /** Constructs an AlphaFullCPU with the given parameters. */
-    AlphaFullCPU(Params *params);
+    /** Constructs an AlphaO3CPU with the given parameters. */
+    AlphaO3CPU(Params *params);
 
     /**
-     * Derived ThreadContext class for use with the AlphaFullCPU.  It
+     * Derived ThreadContext class for use with the AlphaO3CPU.  It
      * provides the interface for any external objects to access a
      * single thread's state and some general CPU state.  Any time
      * external objects try to update state through this interface,
      * the CPU will create an event to squash all in-flight
      * instructions in order to ensure state is maintained correctly.
-     * It must be defined specifically for the AlphaFullCPU because
+     * It must be defined specifically for the AlphaO3CPU because
      * not all architectural state is located within the O3ThreadState
      * (such as the commit PC, and registers), and specific actions
      * must be taken when using this interface (such as squashing all
@@ -87,7 +87,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     {
       public:
         /** Pointer to the CPU. */
-        AlphaFullCPU<Impl> *cpu;
+        AlphaO3CPU<Impl> *cpu;
 
         /** Pointer to the thread state that this TC corrseponds to. */
         O3ThreadState<Impl> *thread;