Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.

src/cpu/base_dyn_inst.cc:
    Delete the allocated data in destructor.
src/cpu/base_dyn_inst.hh:
    Only copy the addresses if the translation succeeded.
src/cpu/o3/alpha_cpu.hh:
    Return actual translating port.
    Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes.
src/cpu/o3/alpha_cpu_impl.hh:
    Pass in memobject to the thread state in SE mode.
src/cpu/o3/commit_impl.hh:
    Initialize all variables.
src/cpu/o3/decode_impl.hh:
    Handle early resolution of branches properly.
src/cpu/o3/fetch.hh:
    Switch structure back to requests.
src/cpu/o3/fetch_impl.hh:
    Initialize all variables, create/delete requests properly.
src/cpu/o3/lsq_unit.hh:
    Include sender state along with the packet.  Also include a more generic writeback event that's only used for stores forwarding data to loads.
src/cpu/o3/lsq_unit_impl.hh:
    Redo writeback code to support the response path of the memory system.
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit_impl.hh:
    Wrap variables in #ifdefs.
src/cpu/o3/store_set.cc:
    Include to get panic() function.
src/cpu/o3/thread_state.hh:
    Create with MemObject as well.
src/cpu/thread_state.hh:
    Have a translating port in the thread state object.
src/python/m5/objects/AlphaFullCPU.py:
    Mem parameter no longer needed.

--HG--
extra : convert_revision : a99381fb25cb183322882ce20935a6f3d1f2b64d

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 2e5c856a8..3c16c3b2e 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -96,7 +96,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         /** Reads this CPU's ID. */
         virtual int readCpuId() { return cpu->cpu_id; }
 
-        virtual TranslatingPort *getMemPort() { return /*thread->port*/ NULL; }
+        virtual TranslatingPort *getMemPort() { return thread->port; }
 
 #if FULL_SYSTEM
         /** Returns a pointer to the system. */
@@ -226,7 +226,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         }
 
         virtual void setNextNPC(uint64_t val)
-        { panic("Alpha has no NextNPC!"); }
+        { }
 
         /** Reads a miscellaneous register. */
         virtual MiscReg readMiscReg(int misc_reg)