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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-17 17:17:43 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-17 17:17:43 -0400 |
commit | 8a1298822182c0ca01caddaa539bdb6a53927e57 (patch) | |
tree | 5677d2b7bf3a3d18295041167f1544def27f957c /src/cpu/o3/alpha_dyn_inst.hh | |
parent | b1fc43dd595e8f0420d9b61932c99f620df237a5 (diff) | |
parent | d96d28e56d39eec0baa1377779119495cfbf4701 (diff) | |
download | gem5-8a1298822182c0ca01caddaa539bdb6a53927e57.tar.xz |
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : c8670f1a39d6826870ca0934587f4cc71c94b0ab
Diffstat (limited to 'src/cpu/o3/alpha_dyn_inst.hh')
-rw-r--r-- | src/cpu/o3/alpha_dyn_inst.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha_dyn_inst.hh index 36a08c4a7..464e53e9d 100644 --- a/src/cpu/o3/alpha_dyn_inst.hh +++ b/src/cpu/o3/alpha_dyn_inst.hh @@ -51,7 +51,7 @@ class AlphaDynInst : public BaseDynInst<Impl> { public: /** Typedef for the CPU. */ - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; @@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst<Impl> public: /** BaseDynInst constructor given a binary instruction. */ AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, - FullCPU *cpu); + O3CPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ AlphaDynInst(StaticInstPtr &_staticInst); |