Make O3CPU model independent of the ISA

Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e

1 files changed, 0 insertions, 179 deletions

diff --git a/src/cpu/o3/alpha_params.hh b/src/cpu/o3/alpha_params.hh
deleted file mode 100644
index f0732733e..000000000
--- a/src/cpu/o3/alpha_params.hh
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_PARAMS_HH__
-#define __CPU_O3_ALPHA_PARAMS_HH__
-
-#include "cpu/o3/cpu.hh"
-
-//Forward declarations
-class AlphaDTB;
-class AlphaITB;
-class FUPool;
-class MemObject;
-class Process;
-class System;
-
-/**
- * This file defines the parameters that will be used for the AlphaO3CPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-
-class AlphaSimpleParams : public BaseO3CPU::Params
-{
-  public:
-
-#if FULL_SYSTEM
-    AlphaITB *itb; AlphaDTB *dtb;
-#else
-    std::vector<Process *> workload;
-    Process *process;
-#endif // FULL_SYSTEM
-
-    MemObject *mem;
-
-    BaseCPU *checker;
-
-    unsigned activity;
-
-    //
-    // Caches
-    //
-//    MemInterface *icacheInterface;
-//    MemInterface *dcacheInterface;
-
-    unsigned cachePorts;
-
-    //
-    // Fetch
-    //
-    unsigned decodeToFetchDelay;
-    unsigned renameToFetchDelay;
-    unsigned iewToFetchDelay;
-    unsigned commitToFetchDelay;
-    unsigned fetchWidth;
-
-    //
-    // Decode
-    //
-    unsigned renameToDecodeDelay;
-    unsigned iewToDecodeDelay;
-    unsigned commitToDecodeDelay;
-    unsigned fetchToDecodeDelay;
-    unsigned decodeWidth;
-
-    //
-    // Rename
-    //
-    unsigned iewToRenameDelay;
-    unsigned commitToRenameDelay;
-    unsigned decodeToRenameDelay;
-    unsigned renameWidth;
-
-    //
-    // IEW
-    //
-    unsigned commitToIEWDelay;
-    unsigned renameToIEWDelay;
-    unsigned issueToExecuteDelay;
-    unsigned issueWidth;
-    FUPool *fuPool;
-
-    //
-    // Commit
-    //
-    unsigned iewToCommitDelay;
-    unsigned renameToROBDelay;
-    unsigned commitWidth;
-    unsigned squashWidth;
-    Tick trapLatency;
-    Tick fetchTrapLatency;
-
-    //
-    // Branch predictor (BP, BTB, RAS)
-    //
-    std::string predType;
-    unsigned localPredictorSize;
-    unsigned localCtrBits;
-    unsigned localHistoryTableSize;
-    unsigned localHistoryBits;
-    unsigned globalPredictorSize;
-    unsigned globalCtrBits;
-    unsigned globalHistoryBits;
-    unsigned choicePredictorSize;
-    unsigned choiceCtrBits;
-
-    unsigned BTBEntries;
-    unsigned BTBTagSize;
-
-    unsigned RASSize;
-
-    //
-    // Load store queue
-    //
-    unsigned LQEntries;
-    unsigned SQEntries;
-
-    //
-    // Memory dependence
-    //
-    unsigned SSITSize;
-    unsigned LFSTSize;
-
-    //
-    // Miscellaneous
-    //
-    unsigned numPhysIntRegs;
-    unsigned numPhysFloatRegs;
-    unsigned numIQEntries;
-    unsigned numROBEntries;
-
-    //SMT Parameters
-    unsigned smtNumFetchingThreads;
-
-    std::string   smtFetchPolicy;
-
-    std::string   smtIQPolicy;
-    unsigned smtIQThreshold;
-
-    std::string   smtLSQPolicy;
-    unsigned smtLSQThreshold;
-
-    std::string   smtCommitPolicy;
-
-    std::string   smtROBPolicy;
-    unsigned smtROBThreshold;
-
-    // Probably can get this from somewhere.
-    unsigned instShiftAmt;
-};
-
-#endif // __CPU_O3_ALPHA_PARAMS_HH__