summaryrefslogtreecommitdiff
path: root/src/cpu/o3/bpred_unit_impl.hh
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2012-09-07 14:20:53 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-09-07 14:20:53 -0500
commit03ff6120540977e02284d1b49845b3081efa164e (patch)
tree37871f81a28700e83bd30917b8af8811ce3521f1 /src/cpu/o3/bpred_unit_impl.hh
parent2059c01673b6fd4d03048e21ee7feef7ae89ee37 (diff)
downloadgem5-03ff6120540977e02284d1b49845b3081efa164e.tar.xz
O3: Get rid of incorrect assert in RAS.
Diffstat (limited to 'src/cpu/o3/bpred_unit_impl.hh')
-rw-r--r--src/cpu/o3/bpred_unit_impl.hh2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 6f0e5e3e0..7231d8f8c 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -207,8 +207,6 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid)
predict_record.RASIndex = RAS[tid].topIdx();
predict_record.RASTarget = rasTop;
- assert(predict_record.RASIndex < 16);
-
RAS[tid].pop();
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s is a return, "