add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a

1 files changed, 6 insertions, 6 deletions

diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index e4e656632..477c8e4cb 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -29,6 +29,7 @@
  */
 
 #include "arch/types.hh"
+#include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "cpu/o3/bpred_unit.hh"
@@ -197,10 +198,10 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
             ++BTBLookups;
 
             if (inst->isCall()) {
-#if THE_ISA == ALPHA_ISA
-                Addr ras_pc = PC + sizeof(MachInst); // Next PC
-#else
+#if ISA_HAS_DELAY_SLOT
                 Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
+#else
+                Addr ras_pc = PC + sizeof(MachInst); // Next PC
 #endif
                 RAS[tid].push(ras_pc);
 
@@ -209,8 +210,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
                 predict_record.wasCall = true;
 
                 DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
-                        ", adding %#x to the RAS.\n",
-                        tid, inst->readPC(), ras_pc);
+                        ", adding %#x to the RAS index: %i.\n",
+                        tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
             }
 
             if (BTB.valid(PC, tid)) {
@@ -283,7 +284,6 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
 
             RAS[tid].restore(pred_hist.front().RASIndex,
                              pred_hist.front().RASTarget);
-
         } else if (pred_hist.front().wasCall) {
             DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry "
                     "added to the RAS.\n",tid);