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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
| commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
| tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/cpu/o3/checker_builder.cc | |
| parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
| download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz | |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/cpu/o3/checker_builder.cc')
| -rw-r--r-- | src/cpu/o3/checker_builder.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 02c817499..8b028e3a0 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -67,8 +67,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param<Tick> progress_interval; #if FULL_SYSTEM - SimObjectParam<AlphaITB *> itb; - SimObjectParam<AlphaDTB *> dtb; + SimObjectParam<TheISA::ITB *> itb; + SimObjectParam<TheISA::DTB *> dtb; SimObjectParam<System *> system; Param<int> cpu_id; Param<Tick> profile; |