diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 05:51:18 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-06 05:51:18 -0500 |
| commit | 20340b5e26e05edd364eda5f69949cc8f957921b (patch) | |
| tree | 8016afd4da57f0f313a08ba56805aa34419086dd /src/cpu/o3/comm.hh | |
| parent | 8a21635effac179a81b618cab3df7d028999e84f (diff) | |
| download | gem5-20340b5e26e05edd364eda5f69949cc8f957921b.tar.xz | |
Change how optional delay slot instructions are detected and squashed.
--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
Diffstat (limited to 'src/cpu/o3/comm.hh')
| -rw-r--r-- | src/cpu/o3/comm.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index aa58fc20e..4683c77af 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -87,7 +87,7 @@ struct DefaultIEWDefaultCommit { bool squash[Impl::MaxThreads]; bool branchMispredict[Impl::MaxThreads]; bool branchTaken[Impl::MaxThreads]; - bool condDelaySlotBranch[Impl::MaxThreads]; + bool squashDelaySlot[Impl::MaxThreads]; uint64_t mispredPC[Impl::MaxThreads]; uint64_t nextPC[Impl::MaxThreads]; InstSeqNum squashedSeqNum[Impl::MaxThreads]; |