O3: Fix mispredicts from non control instructions.

The squash inside the fetch unit should not attempt to remove them from the
branch predictor as non-control instructions are not pushed into the predictor.

1 files changed, 4 insertions, 1 deletions

diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index c9fb3319b..897807fdb 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -87,6 +87,7 @@ struct DefaultIEWDefaultCommit {
 
     bool squash[Impl::MaxThreads];
     bool branchMispredict[Impl::MaxThreads];
+    DynInstPtr mispredictInst[Impl::MaxThreads];
     bool branchTaken[Impl::MaxThreads];
     Addr mispredPC[Impl::MaxThreads];
     TheISA::PCState pc[Impl::MaxThreads];
@@ -107,6 +108,7 @@ struct IssueStruct {
 /** Struct that defines all backwards communication. */
 template<class Impl>
 struct TimeBufStruct {
+    typedef typename Impl::DynInstPtr DynInstPtr;
     struct decodeComm {
         bool squash;
         bool predIncorrect;
@@ -117,6 +119,7 @@ struct TimeBufStruct {
         // @todo: Might want to package this kind of branch stuff into a single
         // struct as it is used pretty frequently.
         bool branchMispredict;
+        DynInstPtr mispredictInst;
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState nextPC;
@@ -156,6 +159,7 @@ struct TimeBufStruct {
         bool robSquashing;
 
         bool branchMispredict;
+        DynInstPtr mispredictInst;
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState pc;
@@ -175,7 +179,6 @@ struct TimeBufStruct {
         InstSeqNum nonSpecSeqNum;
 
         // Hack for now to send back an uncached access to the IEW stage.
-        typedef typename Impl::DynInstPtr DynInstPtr;
         bool uncached;
         DynInstPtr uncachedLoad;