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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-07-26 03:40:56 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-07-26 03:40:56 -0400 |
| commit | e081615cd9d6a41b329fb6a695145152644695b8 (patch) | |
| tree | 7d84d19e2425dad50af3db1ea7e28cd01db0c679 /src/cpu/o3/comm.hh | |
| parent | 887e00f18d9ef7d9a293d004617901949aec5b63 (diff) | |
| download | gem5-e081615cd9d6a41b329fb6a695145152644695b8.tar.xz | |
Now ignore sigaction
src/arch/sparc/isa/operands.isa:
Added the GSR register as a control register
--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
Diffstat (limited to 'src/cpu/o3/comm.hh')
0 files changed, 0 insertions, 0 deletions