mem, cpu: Add a separate flag for strictly ordered memory

The Request::UNCACHEABLE flag currently has two different
functions. The first, and obvious, function is to prevent the memory
system from caching data in the request. The second function is to
prevent reordering and speculation in CPU models.

This changeset gives the order/speculation requirement a separate flag
(Request::STRICT_ORDER). This flag prevents CPU models from doing the
following optimizations:

    * Speculation: CPU models are not allowed to issue speculative
      loads.

    * Write combining: CPU models and caches are not allowed to merge
      writes to the same cache line.

Note: The memory system may still reorder accesses unless the
UNCACHEABLE flag is set. It is therefore expected that the
STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent
this behavior.

1 files changed, 6 insertions, 4 deletions

diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index a425484f5..4da251104 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -185,8 +185,9 @@ struct TimeBufStruct {
         /// Instruction that caused the a non-mispredict squash
         DynInstPtr squashInst; // *F
 
-        /// Hack for now to send back an uncached access to the IEW stage.
-        DynInstPtr uncachedLoad; // *I
+        /// Hack for now to send back a strictly ordered access to the
+        /// IEW stage.
+        DynInstPtr strictlyOrderedLoad; // *I
 
         /// Communication specifically to the IQ to tell the IQ that it can
         /// schedule a non-speculative instruction.
@@ -216,8 +217,9 @@ struct TimeBufStruct {
         /// If the interrupt ended up being cleared before being handled
         bool clearInterrupt; // *F
 
-        /// Hack for now to send back an uncached access to the IEW stage.
-        bool uncached; // *I
+        /// Hack for now to send back an strictly ordered access to
+        /// the IEW stage.
+        bool strictlyOrdered; // *I
 
     };