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authorGabe Black <gblack@eecs.umich.edu>2007-04-14 17:13:18 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-14 17:13:18 +0000
commitc3081d9c1c36e1a08c173048783d191fa19463de (patch)
treef2717bd70d64af1e6ef54ff73e3cbee7984f4b31 /src/cpu/o3/comm.hh
parent5a3dcc172a9fd661330909815b163eb6f4d6a2d8 (diff)
downloadgem5-c3081d9c1c36e1a08c173048783d191fa19463de.tar.xz
Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
--HG-- extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
Diffstat (limited to 'src/cpu/o3/comm.hh')
-rw-r--r--src/cpu/o3/comm.hh21
1 files changed, 12 insertions, 9 deletions
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 8d7bb95f4..fb772060b 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -87,9 +87,10 @@ struct DefaultIEWDefaultCommit {
bool squash[Impl::MaxThreads];
bool branchMispredict[Impl::MaxThreads];
bool branchTaken[Impl::MaxThreads];
- uint64_t mispredPC[Impl::MaxThreads];
- uint64_t nextPC[Impl::MaxThreads];
- uint64_t nextNPC[Impl::MaxThreads];
+ Addr mispredPC[Impl::MaxThreads];
+ Addr nextPC[Impl::MaxThreads];
+ Addr nextNPC[Impl::MaxThreads];
+ Addr nextMicroPC[Impl::MaxThreads];
InstSeqNum squashedSeqNum[Impl::MaxThreads];
bool includeSquashInst[Impl::MaxThreads];
@@ -118,9 +119,10 @@ struct TimeBufStruct {
// struct as it is used pretty frequently.
bool branchMispredict;
bool branchTaken;
- uint64_t mispredPC;
- uint64_t nextPC;
- uint64_t nextNPC;
+ Addr mispredPC;
+ Addr nextPC;
+ Addr nextNPC;
+ Addr nextMicroPC;
unsigned branchCount;
};
@@ -158,9 +160,10 @@ struct TimeBufStruct {
bool branchMispredict;
bool branchTaken;
- uint64_t mispredPC;
- uint64_t nextPC;
- uint64_t nextNPC;
+ Addr mispredPC;
+ Addr nextPC;
+ Addr nextNPC;
+ Addr nextMicroPC;
// Represents the instruction that has either been retired or
// squashed. Similar to having a single bus that broadcasts the