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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 16:13:53 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 16:13:53 -0700 |
commit | ed1db23b414a372a012d406d5a684775f00baa11 (patch) | |
tree | 1c706f022e2b84be0a01e5bc577075ba30276011 /src/cpu/o3/comm.hh | |
parent | 4d1bcbcd36e5735e76b38abb151de716c31a2272 (diff) | |
parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
download | gem5-ed1db23b414a372a012d406d5a684775f00baa11.tar.xz |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
Diffstat (limited to 'src/cpu/o3/comm.hh')
-rw-r--r-- | src/cpu/o3/comm.hh | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index d96919007..fb772060b 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -87,10 +87,10 @@ struct DefaultIEWDefaultCommit { bool squash[Impl::MaxThreads]; bool branchMispredict[Impl::MaxThreads]; bool branchTaken[Impl::MaxThreads]; - bool squashDelaySlot[Impl::MaxThreads]; - uint64_t mispredPC[Impl::MaxThreads]; - uint64_t nextPC[Impl::MaxThreads]; - uint64_t nextNPC[Impl::MaxThreads]; + Addr mispredPC[Impl::MaxThreads]; + Addr nextPC[Impl::MaxThreads]; + Addr nextNPC[Impl::MaxThreads]; + Addr nextMicroPC[Impl::MaxThreads]; InstSeqNum squashedSeqNum[Impl::MaxThreads]; bool includeSquashInst[Impl::MaxThreads]; @@ -114,15 +114,15 @@ struct TimeBufStruct { uint64_t branchAddr; InstSeqNum doneSeqNum; - InstSeqNum bdelayDoneSeqNum; // @todo: Might want to package this kind of branch stuff into a single // struct as it is used pretty frequently. bool branchMispredict; bool branchTaken; - uint64_t mispredPC; - uint64_t nextPC; - uint64_t nextNPC; + Addr mispredPC; + Addr nextPC; + Addr nextNPC; + Addr nextMicroPC; unsigned branchCount; }; @@ -160,18 +160,16 @@ struct TimeBufStruct { bool branchMispredict; bool branchTaken; - uint64_t mispredPC; - uint64_t nextPC; - uint64_t nextNPC; + Addr mispredPC; + Addr nextPC; + Addr nextNPC; + Addr nextMicroPC; // Represents the instruction that has either been retired or // squashed. Similar to having a single bus that broadcasts the // retired or squashed sequence number. InstSeqNum doneSeqNum; - InstSeqNum bdelayDoneSeqNum; - bool squashDelaySlot; - //Just in case we want to do a commit/squash on a cycle //(necessary for multiple ROBs?) bool commitInsts; |