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authorAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:07 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:07 -0500
commitb84bd3028c173893101c0c0c188e5f5b16e4fdee (patch)
treedbf8680bc399db9321133d50e410a94833a17f78 /src/cpu/o3/commit.hh
parentd4eca0591d28cd34448148302cb26872bfc1f919 (diff)
downloadgem5-b84bd3028c173893101c0c0c188e5f5b16e4fdee.tar.xz
cpu: Fix a livelock in the o3 cpu.
Check if an instruction just enabled interrupts and we've previously had an interrupt pending that was not handled because interrupts were subsequently disabled before the pipeline reached a place to handle the interrupt. In that case squash now to make sure the interrupt is handled.
Diffstat (limited to 'src/cpu/o3/commit.hh')
-rw-r--r--src/cpu/o3/commit.hh6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index c76d6c1d0..62aa274c2 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -479,6 +479,12 @@ class DefaultCommit
/** True if last committed microop can be followed by an interrupt */
bool canHandleInterrupts;
+ /** Have we had an interrupt pending and then seen it de-asserted because
+ of a masking change? In this case the variable is set and the next time
+ interrupts are enabled and pending the pipeline will squash to avoid
+ a possible livelock senario. */
+ bool avoidQuiesceLiveLock;
+
/** Updates commit stats based on this instruction. */
void updateComInstStats(DynInstPtr &inst);