Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)

Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7

1 files changed, 13 insertions, 1 deletions

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 0b31cb9c8..c73b39ec6 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #ifndef __CPU_O3_COMMIT_HH__
@@ -280,12 +281,20 @@ class DefaultCommit
     /** Sets the PC of a specific thread. */
     void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
 
-    /** Reads the PC of a specific thread. */
+    /** Reads the next PC of a specific thread. */
     uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
 
     /** Sets the next PC of a specific thread. */
     void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
 
+#if THE_ISA != ALPHA_ISA
+    /** Reads the next NPC of a specific thread. */
+    uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; }
+
+    /** Sets the next NPC of a specific thread. */
+    void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
+#endif
+
   private:
     /** Time buffer interface. */
     TimeBuffer<TimeStruct> *timeBuffer;
@@ -397,6 +406,9 @@ class DefaultCommit
     /** The next PC of each thread. */
     Addr nextPC[Impl::MaxThreads];
 
+    /** The next NPC of each thread. */
+    Addr nextNPC[Impl::MaxThreads];
+
     /** The sequence number of the youngest valid instruction in the ROB. */
     InstSeqNum youngestSeqNum[Impl::MaxThreads];