MIPS ISA runs 'hello world' in O3CPU ...

src/arch/mips/isa/base.isa:
    special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
    add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
    Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
    Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
    Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
    change comment

--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5

1 files changed, 6 insertions, 0 deletions

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index cb83012f7..5caa317b3 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -165,6 +165,9 @@ class DefaultCommit
     /** Sets the pointer to the IEW stage. */
     void setIEWStage(IEW *iew_stage);
 
+    /** Skid buffer between rename and commit. */
+    std::queue<DynInstPtr> skidBuffer;
+
     /** The pointer to the IEW stage. Used solely to ensure that
      * various events (traps, interrupts, syscalls) do not occur until
      * all stores have written back.
@@ -256,6 +259,9 @@ class DefaultCommit
     /** Gets instructions from rename and inserts them into the ROB. */
     void getInsts();
 
+    /** Insert all instructions from rename into skidBuffer */
+    void skidInsert();
+
     /** Marks completed instructions using information sent from IEW. */
     void markCompletedInsts();