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| author | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
|---|---|---|
| committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
| commit | 0b3897fc90901953e9d016466c37ab507f85023c (patch) | |
| tree | 0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/cpu/o3/commit_impl.hh | |
| parent | 5a648f2074caad8aee97e03f27e8eecc527a2cba (diff) | |
| download | gem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz | |
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 45f5bc02b..31398c3d9 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -631,7 +631,8 @@ DefaultCommit<Impl>::tick() wroteToTimeBuffer = false; _nextStatus = Inactive; - if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { + if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() && + interrupt == NoFault) { cpu->signalDrained(); drainPending = false; return; |