Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 3d951bbeee0178de47e1bdbe704808544bfe732e

1 files changed, 1026 insertions, 221 deletions

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e289bc0c0..346a8bc1c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,26 +26,112 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <algorithm>
+#include <string>
+
+#include "base/loader/symtab.hh"
 #include "base/timebuf.hh"
-#include "cpu/o3/commit.hh"
+#include "cpu/checker/cpu.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/o3/commit.hh"
+#include "cpu/o3/thread_state.hh"
+
+using namespace std;
 
 template <class Impl>
-SimpleCommit<Impl>::SimpleCommit(Params &params)
-    : dcacheInterface(params.dcacheInterface),
-      iewToCommitDelay(params.iewToCommitDelay),
-      renameToROBDelay(params.renameToROBDelay),
-      renameWidth(params.renameWidth),
-      iewWidth(params.executeWidth),
-      commitWidth(params.commitWidth)
+DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
+                                          unsigned _tid)
+    : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
 {
-    _status = Idle;
+    this->setFlags(Event::AutoDelete);
 }
 
 template <class Impl>
 void
-SimpleCommit<Impl>::regStats()
+DefaultCommit<Impl>::TrapEvent::process()
+{
+    // This will get reset by commit if it was switched out at the
+    // time of this event processing.
+    commit->trapSquash[tid] = true;
+}
+
+template <class Impl>
+const char *
+DefaultCommit<Impl>::TrapEvent::description()
+{
+    return "Trap event";
+}
+
+template <class Impl>
+DefaultCommit<Impl>::DefaultCommit(Params *params)
+    : dcacheInterface(params->dcacheInterface),
+      squashCounter(0),
+      iewToCommitDelay(params->iewToCommitDelay),
+      commitToIEWDelay(params->commitToIEWDelay),
+      renameToROBDelay(params->renameToROBDelay),
+      fetchToCommitDelay(params->commitToFetchDelay),
+      renameWidth(params->renameWidth),
+      iewWidth(params->executeWidth),
+      commitWidth(params->commitWidth),
+      numThreads(params->numberOfThreads),
+      switchedOut(false),
+      trapLatency(params->trapLatency),
+      fetchTrapLatency(params->fetchTrapLatency)
 {
+    _status = Active;
+    _nextStatus = Inactive;
+    string policy = params->smtCommitPolicy;
+
+    //Convert string to lowercase
+    std::transform(policy.begin(), policy.end(), policy.begin(),
+                   (int(*)(int)) tolower);
+
+    //Assign commit policy
+    if (policy == "aggressive"){
+        commitPolicy = Aggressive;
+
+        DPRINTF(Commit,"Commit Policy set to Aggressive.");
+    } else if (policy == "roundrobin"){
+        commitPolicy = RoundRobin;
+
+        //Set-Up Priority List
+        for (int tid=0; tid < numThreads; tid++) {
+            priority_list.push_back(tid);
+        }
+
+        DPRINTF(Commit,"Commit Policy set to Round Robin.");
+    } else if (policy == "oldestready"){
+        commitPolicy = OldestReady;
+
+        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
+    } else {
+        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
+               "RoundRobin,OldestReady}");
+    }
+
+    for (int i=0; i < numThreads; i++) {
+        commitStatus[i] = Idle;
+        changedROBNumEntries[i] = false;
+        trapSquash[i] = false;
+        xcSquash[i] = false;
+    }
+
+    fetchFaultTick = 0;
+    fetchTrapWait = 0;
+}
+
+template <class Impl>
+std::string
+DefaultCommit<Impl>::name() const
+{
+    return cpu->name() + ".commit";
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::regStats()
+{
+    using namespace Stats;
     commitCommittedInsts
         .name(name() + ".commitCommittedInsts")
         .desc("The number of committed instructions")
@@ -63,41 +149,110 @@ SimpleCommit<Impl>::regStats()
         .desc("The number of times commit has been forced to stall to "
               "communicate backwards")
         .prereq(commitNonSpecStalls);
-    commitCommittedBranches
-        .name(name() + ".commitCommittedBranches")
-        .desc("The number of committed branches")
-        .prereq(commitCommittedBranches);
-    commitCommittedLoads
-        .name(name() + ".commitCommittedLoads")
-        .desc("The number of committed loads")
-        .prereq(commitCommittedLoads);
-    commitCommittedMemRefs
-        .name(name() + ".commitCommittedMemRefs")
-        .desc("The number of committed memory references")
-        .prereq(commitCommittedMemRefs);
     branchMispredicts
         .name(name() + ".branchMispredicts")
         .desc("The number of times a branch was mispredicted")
         .prereq(branchMispredicts);
-    n_committed_dist
+    numCommittedDist
         .init(0,commitWidth,1)
         .name(name() + ".COM:committed_per_cycle")
         .desc("Number of insts commited each cycle")
         .flags(Stats::pdf)
         ;
+
+    statComInst
+        .init(cpu->number_of_threads)
+        .name(name() + ".COM:count")
+        .desc("Number of instructions committed")
+        .flags(total)
+        ;
+
+    statComSwp
+        .init(cpu->number_of_threads)
+        .name(name() + ".COM:swp_count")
+        .desc("Number of s/w prefetches committed")
+        .flags(total)
+        ;
+
+    statComRefs
+        .init(cpu->number_of_threads)
+        .name(name() +  ".COM:refs")
+        .desc("Number of memory references committed")
+        .flags(total)
+        ;
+
+    statComLoads
+        .init(cpu->number_of_threads)
+        .name(name() +  ".COM:loads")
+        .desc("Number of loads committed")
+        .flags(total)
+        ;
+
+    statComMembars
+        .init(cpu->number_of_threads)
+        .name(name() +  ".COM:membars")
+        .desc("Number of memory barriers committed")
+        .flags(total)
+        ;
+
+    statComBranches
+        .init(cpu->number_of_threads)
+        .name(name() + ".COM:branches")
+        .desc("Number of branches committed")
+        .flags(total)
+        ;
+
+    //
+    //  Commit-Eligible instructions...
+    //
+    //  -> The number of instructions eligible to commit in those
+    //  cycles where we reached our commit BW limit (less the number
+    //  actually committed)
+    //
+    //  -> The average value is computed over ALL CYCLES... not just
+    //  the BW limited cycles
+    //
+    //  -> The standard deviation is computed only over cycles where
+    //  we reached the BW limit
+    //
+    commitEligible
+        .init(cpu->number_of_threads)
+        .name(name() + ".COM:bw_limited")
+        .desc("number of insts not committed due to BW limits")
+        .flags(total)
+        ;
+
+    commitEligibleSamples
+        .name(name() + ".COM:bw_lim_events")
+        .desc("number cycles where commit BW limit reached")
+        ;
 }
 
 template <class Impl>
 void
-SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
 {
     DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
     cpu = cpu_ptr;
+
+    // Commit must broadcast the number of free entries it has at the start of
+    // the simulation, so it starts as active.
+    cpu->activateStage(FullCPU::CommitIdx);
+
+    trapLatency = cpu->cycles(trapLatency);
+    fetchTrapLatency = cpu->cycles(fetchTrapLatency);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
+{
+    thread = threads;
 }
 
 template <class Impl>
 void
-SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 {
     DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
     timeBuffer = tb_ptr;
@@ -111,7 +266,18 @@ SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
 
 template <class Impl>
 void
-SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
+DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
+{
+    DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
+    fetchQueue = fq_ptr;
+
+    // Setup wire to get instructions from rename (for the ROB).
+    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 {
     DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
     renameQueue = rq_ptr;
@@ -122,7 +288,7 @@ SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
 
 template <class Impl>
 void
-SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
+DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 {
     DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
     iewQueue = iq_ptr;
@@ -133,7 +299,40 @@ SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
 
 template <class Impl>
 void
-SimpleCommit<Impl>::setROB(ROB *rob_ptr)
+DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
+{
+    fetchStage = fetch_stage;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
+{
+    iewStage = iew_stage;
+}
+
+template<class Impl>
+void
+DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+    DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
+    activeThreads = at_ptr;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
+{
+    DPRINTF(Commit, "Setting rename map pointers.\n");
+
+    for (int i=0; i < numThreads; i++) {
+        renameMap[i] = &rm_ptr[i];
+    }
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setROB(ROB *rob_ptr)
 {
     DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
     rob = rob_ptr;
@@ -141,107 +340,451 @@ SimpleCommit<Impl>::setROB(ROB *rob_ptr)
 
 template <class Impl>
 void
-SimpleCommit<Impl>::tick()
-{
-    // If the ROB is currently in its squash sequence, then continue
-    // to squash.  In this case, commit does not do anything.  Otherwise
-    // run commit.
-    if (_status == ROBSquashing) {
-        if (rob->isDoneSquashing()) {
-            _status = Running;
-        } else {
-            rob->doSquash();
-
-            // Send back sequence number of tail of ROB, so other stages
-            // can squash younger instructions.  Note that really the only
-            // stage that this is important for is the IEW stage; other
-            // stages can just clear all their state as long as selective
-            // replay isn't used.
-            toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
-            toIEW->commitInfo.robSquashing = true;
+DefaultCommit<Impl>::initStage()
+{
+    rob->setActiveThreads(activeThreads);
+    rob->resetEntries();
+
+    // Broadcast the number of free entries.
+    for (int i=0; i < numThreads; i++) {
+        toIEW->commitInfo[i].usedROB = true;
+        toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
+    }
+
+    cpu->activityThisCycle();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::switchOut()
+{
+    switchPending = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::doSwitchOut()
+{
+    switchedOut = true;
+    switchPending = false;
+    rob->switchOut();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::takeOverFrom()
+{
+    switchedOut = false;
+    _status = Active;
+    _nextStatus = Inactive;
+    for (int i=0; i < numThreads; i++) {
+        commitStatus[i] = Idle;
+        changedROBNumEntries[i] = false;
+        trapSquash[i] = false;
+        xcSquash[i] = false;
+    }
+    squashCounter = 0;
+    rob->takeOverFrom();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::updateStatus()
+{
+    // reset ROB changed variable
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+        changedROBNumEntries[tid] = false;
+
+        // Also check if any of the threads has a trap pending
+        if (commitStatus[tid] == TrapPending ||
+            commitStatus[tid] == FetchTrapPending) {
+            _nextStatus = Active;
         }
-    } else {
-        commit();
     }
 
+    if (_nextStatus == Inactive && _status == Active) {
+        DPRINTF(Activity, "Deactivating stage.\n");
+        cpu->deactivateStage(FullCPU::CommitIdx);
+    } else if (_nextStatus == Active && _status == Inactive) {
+        DPRINTF(Activity, "Activating stage.\n");
+        cpu->activateStage(FullCPU::CommitIdx);
+    }
+
+    _status = _nextStatus;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setNextStatus()
+{
+    int squashes = 0;
+
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (commitStatus[tid] == ROBSquashing) {
+            squashes++;
+        }
+    }
+
+    assert(squashes == squashCounter);
+
+    // If commit is currently squashing, then it will have activity for the
+    // next cycle. Set its next status as active.
+    if (squashCounter) {
+        _nextStatus = Active;
+    }
+}
+
+template <class Impl>
+bool
+DefaultCommit<Impl>::changedROBEntries()
+{
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (changedROBNumEntries[tid]) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+template <class Impl>
+unsigned
+DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
+{
+    return rob->numFreeEntries(tid);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
+{
+    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
+
+    TrapEvent *trap = new TrapEvent(this, tid);
+
+    trap->schedule(curTick + trapLatency);
+
+    thread[tid]->trapPending = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::generateXCEvent(unsigned tid)
+{
+    DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
+
+    xcSquash[tid] = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashAll(unsigned tid)
+{
+    // If we want to include the squashing instruction in the squash,
+    // then use one older sequence number.
+    // Hopefully this doesn't mess things up.  Basically I want to squash
+    // all instructions of this thread.
+    InstSeqNum squashed_inst = rob->isEmpty() ?
+        0 : rob->readHeadInst(tid)->seqNum - 1;;
+
+    // All younger instructions will be squashed. Set the sequence
+    // number as the youngest instruction in the ROB (0 in this case.
+    // Hopefully nothing breaks.)
+    youngestSeqNum[tid] = 0;
+
+    rob->squash(squashed_inst, tid);
+    changedROBNumEntries[tid] = true;
+
+    // Send back the sequence number of the squashed instruction.
+    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
+
+    // Send back the squash signal to tell stages that they should
+    // squash.
+    toIEW->commitInfo[tid].squash = true;
+
+    // Send back the rob squashing signal so other stages know that
+    // the ROB is in the process of squashing.
+    toIEW->commitInfo[tid].robSquashing = true;
+
+    toIEW->commitInfo[tid].branchMispredict = false;
+
+    toIEW->commitInfo[tid].nextPC = PC[tid];
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashFromTrap(unsigned tid)
+{
+    squashAll(tid);
+
+    DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
+
+    thread[tid]->trapPending = false;
+    thread[tid]->inSyscall = false;
+
+    trapSquash[tid] = false;
+
+    commitStatus[tid] = ROBSquashing;
+    cpu->activityThisCycle();
+
+    ++squashCounter;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashFromXC(unsigned tid)
+{
+    squashAll(tid);
+
+    DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
+
+    thread[tid]->inSyscall = false;
+    assert(!thread[tid]->trapPending);
+
+    commitStatus[tid] = ROBSquashing;
+    cpu->activityThisCycle();
+
+    xcSquash[tid] = false;
+
+    ++squashCounter;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::tick()
+{
+    wroteToTimeBuffer = false;
+    _nextStatus = Inactive;
+
+    if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+        cpu->signalSwitched();
+        return;
+    }
+
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+
+    // Check if any of the threads are done squashing.  Change the
+    // status if they are done.
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (commitStatus[tid] == ROBSquashing) {
+
+            if (rob->isDoneSquashing(tid)) {
+                commitStatus[tid] = Running;
+                --squashCounter;
+            } else {
+                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
+                        "insts this cycle.\n", tid);
+            }
+        }
+    }
+
+    commit();
+
     markCompletedInsts();
 
-    // Writeback number of free ROB entries here.
-    DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
-            rob->numFreeEntries());
-    toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
+    threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
+            // The ROB has more instructions it can commit. Its next status
+            // will be active.
+            _nextStatus = Active;
+
+            DynInstPtr inst = rob->readHeadInst(tid);
+
+            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
+                    " ROB and ready to commit\n",
+                    tid, inst->seqNum, inst->readPC());
+
+        } else if (!rob->isEmpty(tid)) {
+            DynInstPtr inst = rob->readHeadInst(tid);
+
+            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
+                    "%#x is head of ROB and not ready\n",
+                    tid, inst->seqNum, inst->readPC());
+        }
+
+        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
+                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
+    }
+
+
+    if (wroteToTimeBuffer) {
+        DPRINTF(Activity, "Activity This Cycle.\n");
+        cpu->activityThisCycle();
+    }
+
+    updateStatus();
 }
 
 template <class Impl>
 void
-SimpleCommit<Impl>::commit()
+DefaultCommit<Impl>::commit()
 {
+
     //////////////////////////////////////
     // Check for interrupts
     //////////////////////////////////////
 
-    // Process interrupts if interrupts are enabled and not in PAL mode.
-    // Take the PC from commit and write it to the IPR, then squash.  The
-    // interrupt completing will take care of restoring the PC from that value
-    // in the IPR.  Look at IPR[EXC_ADDR];
-    // hwrei() is what resets the PC to the place where instruction execution
-    // beings again.
 #if FULL_SYSTEM
-    if (//checkInterrupts &&
+    // Process interrupts if interrupts are enabled, not in PAL mode,
+    // and no other traps or external squashes are currently pending.
+    // @todo: Allow other threads to handle interrupts.
+    if (cpu->checkInterrupts &&
         cpu->check_interrupts() &&
-        !cpu->inPalMode(readCommitPC())) {
-        // Will need to squash all instructions currently in flight and have
-        // the interrupt handler restart at the last non-committed inst.
-        // Most of that can be handled through the trap() function.  The
-        // processInterrupts() function really just checks for interrupts
-        // and then calls trap() if there is an interrupt present.
+        !cpu->inPalMode(readPC()) &&
+        !trapSquash[0] &&
+        !xcSquash[0]) {
+        // Tell fetch that there is an interrupt pending.  This will
+        // make fetch wait until it sees a non PAL-mode PC, at which
+        // point it stops fetching instructions.
+        toIEW->commitInfo[0].interruptPending = true;
+
+        // Wait until the ROB is empty and all stores have drained in
+        // order to enter the interrupt.
+        if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+            // Not sure which thread should be the one to interrupt.  For now
+            // always do thread 0.
+            assert(!thread[0]->inSyscall);
+            thread[0]->inSyscall = true;
+
+            // CPU will handle implementation of the interrupt.
+            cpu->processInterrupts();
+
+            // Now squash or record that I need to squash this cycle.
+            commitStatus[0] = TrapPending;
+
+            // Exit state update mode to avoid accidental updating.
+            thread[0]->inSyscall = false;
+
+            // Generate trap squash event.
+            generateTrapEvent(0);
 
-        // CPU will handle implementation of the interrupt.
-        cpu->processInterrupts();
+            toIEW->commitInfo[0].clearInterrupt = true;
+
+            DPRINTF(Commit, "Interrupt detected.\n");
+        } else {
+            DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
+        }
     }
 #endif // FULL_SYSTEM
 
     ////////////////////////////////////
-    // Check for squash signal, handle that first
+    // Check for any possible squashes, handle them first
     ////////////////////////////////////
 
-    // Want to mainly check if the IEW stage is telling the ROB to squash.
-    // Should I also check if the commit stage is telling the ROB to squah?
-    // This might be necessary to keep the same timing between the IQ and
-    // the ROB...
-    if (fromIEW->squash) {
-        DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
+            // Record the fault.  Wait until it's empty in the ROB.
+            // Then handle the trap.  Ignore it if there's already a
+            // trap pending as fetch will be redirected.
+            fetchFault = fromFetch->fetchFault;
+            fetchFaultTick = curTick + fetchTrapLatency;
+            commitStatus[0] = FetchTrapPending;
+            DPRINTF(Commit, "Fault from fetch recorded.  Will trap if the "
+                    "ROB empties without squashing the fault.\n");
+            fetchTrapWait = 0;
+        }
+
+        // Fetch may tell commit to clear the trap if it's been squashed.
+        if (fromFetch->clearFetchFault) {
+            DPRINTF(Commit, "Received clear fetch fault signal\n");
+            fetchTrapWait = 0;
+            if (commitStatus[0] == FetchTrapPending) {
+                DPRINTF(Commit, "Clearing fault from fetch\n");
+                commitStatus[0] = Running;
+            }
+        }
+
+        // Not sure which one takes priority.  I think if we have
+        // both, that's a bad sign.
+        if (trapSquash[tid] == true) {
+            assert(!xcSquash[tid]);
+            squashFromTrap(tid);
+        } else if (xcSquash[tid] == true) {
+            squashFromXC(tid);
+        }
+
+        // Squashed sequence number must be older than youngest valid
+        // instruction in the ROB. This prevents squashes from younger
+        // instructions overriding squashes from older instructions.
+        if (fromIEW->squash[tid] &&
+            commitStatus[tid] != TrapPending &&
+            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
+
+            DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
+                    tid,
+                    fromIEW->mispredPC[tid],
+                    fromIEW->squashedSeqNum[tid]);
 
-        _status = ROBSquashing;
+            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
+                    tid,
+                    fromIEW->nextPC[tid]);
 
-        InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
+            commitStatus[tid] = ROBSquashing;
 
-        rob->squash(squashed_inst);
+            ++squashCounter;
 
-        // Send back the sequence number of the squashed instruction.
-        toIEW->commitInfo.doneSeqNum = squashed_inst;
+            // If we want to include the squashing instruction in the squash,
+            // then use one older sequence number.
+            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 
-        // Send back the squash signal to tell stages that they should squash.
-        toIEW->commitInfo.squash = true;
+            if (fromIEW->includeSquashInst[tid] == true)
+                squashed_inst--;
 
-        // Send back the rob squashing signal so other stages know that the
-        // ROB is in the process of squashing.
-        toIEW->commitInfo.robSquashing = true;
+            // All younger instructions will be squashed. Set the sequence
+            // number as the youngest instruction in the ROB.
+            youngestSeqNum[tid] = squashed_inst;
 
-        toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
+            rob->squash(squashed_inst, tid);
+            changedROBNumEntries[tid] = true;
 
-        toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
+            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
 
-        toIEW->commitInfo.nextPC = fromIEW->nextPC;
+            toIEW->commitInfo[tid].squash = true;
 
-        toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
+            // Send back the rob squashing signal so other stages know that
+            // the ROB is in the process of squashing.
+            toIEW->commitInfo[tid].robSquashing = true;
 
-        if (toIEW->commitInfo.branchMispredict) {
-            ++branchMispredicts;
+            toIEW->commitInfo[tid].branchMispredict =
+                fromIEW->branchMispredict[tid];
+
+            toIEW->commitInfo[tid].branchTaken =
+                fromIEW->branchTaken[tid];
+
+            toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
+
+            toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
+
+            if (toIEW->commitInfo[tid].branchMispredict) {
+                ++branchMispredicts;
+            }
         }
+
     }
 
-    if (_status != ROBSquashing) {
+    setNextStatus();
+
+    if (squashCounter != numThreads) {
         // If we're not currently squashing, then get instructions.
         getInsts();
 
@@ -249,121 +792,185 @@ SimpleCommit<Impl>::commit()
         commitInsts();
     }
 
-    // If the ROB is empty, we can set this stage to idle.  Use this
-    // in the future when the Idle status will actually be utilized.
-#if 0
-    if (rob->isEmpty()) {
-        DPRINTF(Commit, "Commit: ROB is empty.  Status changed to idle.\n");
-        _status = Idle;
-        // Schedule an event so that commit will actually wake up
-        // once something gets put in the ROB.
+    //Check for any activity
+    threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (changedROBNumEntries[tid]) {
+            toIEW->commitInfo[tid].usedROB = true;
+            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
+
+            if (rob->isEmpty(tid)) {
+                toIEW->commitInfo[tid].emptyROB = true;
+            }
+
+            wroteToTimeBuffer = true;
+            changedROBNumEntries[tid] = false;
+        }
     }
-#endif
 }
 
-// Loop that goes through as many instructions in the ROB as possible and
-// tries to commit them.  The actual work for committing is done by the
-// commitHead() function.
 template <class Impl>
 void
-SimpleCommit<Impl>::commitInsts()
+DefaultCommit<Impl>::commitInsts()
 {
     ////////////////////////////////////
     // Handle commit
-    // Note that commit will be handled prior to the ROB so that the ROB
-    // only tries to commit instructions it has in this current cycle, and
-    // not instructions it is writing in during this cycle.
-    // Can't commit and squash things at the same time...
+    // Note that commit will be handled prior to putting new
+    // instructions in the ROB so that the ROB only tries to commit
+    // instructions it has in this current cycle, and not instructions
+    // it is writing in during this cycle.  Can't commit and squash
+    // things at the same time...
     ////////////////////////////////////
 
-    if (rob->isEmpty())
-        return;
-
-    DynInstPtr head_inst = rob->readHeadInst();
+    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
 
     unsigned num_committed = 0;
 
+    DynInstPtr head_inst;
+
     // Commit as many instructions as possible until the commit bandwidth
     // limit is reached, or it becomes impossible to commit any more.
-    while (!rob->isEmpty() &&
-           head_inst->readyToCommit() &&
-           num_committed < commitWidth)
-    {
-        DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
+    while (num_committed < commitWidth) {
+        int commit_thread = getCommittingThread();
+
+        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
+            break;
+
+        head_inst = rob->readHeadInst(commit_thread);
+
+        int tid = head_inst->threadNumber;
+
+        assert(tid == commit_thread);
+
+        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
+                head_inst->seqNum, tid);
 
-        // If the head instruction is squashed, it is ready to retire at any
-        // time.  However, we need to avoid updating any other state
-        // incorrectly if it's already been squashed.
+        // If the head instruction is squashed, it is ready to retire
+        // (be removed from the ROB) at any time.
         if (head_inst->isSquashed()) {
 
-            DPRINTF(Commit, "Commit: Retiring squashed instruction from "
+            DPRINTF(Commit, "Retiring squashed instruction from "
                     "ROB.\n");
 
-            // Tell ROB to retire head instruction.  This retires the head
-            // inst in the ROB without affecting any other stages.
-            rob->retireHead();
+            rob->retireHead(commit_thread);
 
             ++commitSquashedInsts;
 
+            // Record that the number of ROB entries has changed.
+            changedROBNumEntries[tid] = true;
         } else {
+            PC[tid] = head_inst->readPC();
+            nextPC[tid] = head_inst->readNextPC();
+
             // Increment the total number of non-speculative instructions
             // executed.
             // Hack for now: it really shouldn't happen until after the
             // commit is deemed to be successful, but this count is needed
             // for syscalls.
-            cpu->funcExeInst++;
+            thread[tid]->funcExeInst++;
 
             // Try to commit the head instruction.
             bool commit_success = commitHead(head_inst, num_committed);
 
-            // Update what instruction we are looking at if the commit worked.
             if (commit_success) {
                 ++num_committed;
 
-                // Send back which instruction has been committed.
-                // @todo: Update this later when a wider pipeline is used.
-                // Hmm, can't really give a pointer here...perhaps the
-                // sequence number instead (copy).
-                toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
+                changedROBNumEntries[tid] = true;
+
+                // Set the doneSeqNum to the youngest committed instruction.
+                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
 
                 ++commitCommittedInsts;
 
-                if (!head_inst->isNop()) {
-                    cpu->instDone();
+                // To match the old model, don't count nops and instruction
+                // prefetches towards the total commit count.
+                if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
+                    cpu->instDone(tid);
+                }
+
+                PC[tid] = nextPC[tid];
+                nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
+#if FULL_SYSTEM
+                int count = 0;
+                Addr oldpc;
+                do {
+                    // Debug statement.  Checks to make sure we're not
+                    // currently updating state while handling PC events.
+                    if (count == 0)
+                        assert(!thread[tid]->inSyscall &&
+                               !thread[tid]->trapPending);
+                    oldpc = PC[tid];
+                    cpu->system->pcEventQueue.service(
+                        thread[tid]->getXCProxy());
+                    count++;
+                } while (oldpc != PC[tid]);
+                if (count > 1) {
+                    DPRINTF(Commit, "PC skip function event, stopping commit\n");
+                    break;
                 }
+#endif
             } else {
+                DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
+                        "[tid:%i] [sn:%i].\n",
+                        head_inst->readPC(), tid ,head_inst->seqNum);
                 break;
             }
         }
-
-        // Update the pointer to read the next instruction in the ROB.
-        head_inst = rob->readHeadInst();
     }
 
     DPRINTF(CommitRate, "%i\n", num_committed);
-    n_committed_dist.sample(num_committed);
+    numCommittedDist.sample(num_committed);
+
+    if (num_committed == commitWidth) {
+        commitEligible[0]++;
+    }
 }
 
 template <class Impl>
 bool
-SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
+DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 {
-    // Make sure instruction is valid
     assert(head_inst);
 
-    // If the instruction is not executed yet, then it is a non-speculative
-    // or store inst.  Signal backwards that it should be executed.
+    int tid = head_inst->threadNumber;
+
+    // If the instruction is not executed yet, then it will need extra
+    // handling.  Signal backwards that it should be executed.
     if (!head_inst->isExecuted()) {
         // Keep this number correct.  We have not yet actually executed
         // and committed this instruction.
-        cpu->funcExeInst--;
-
-        if (head_inst->isNonSpeculative()) {
-            DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
-                    "instruction at the head of the ROB, PC %#x.\n",
-                    head_inst->readPC());
+        thread[tid]->funcExeInst--;
+
+        head_inst->reachedCommit = true;
+
+        if (head_inst->isNonSpeculative() ||
+            head_inst->isMemBarrier() ||
+            head_inst->isWriteBarrier()) {
+
+            DPRINTF(Commit, "Encountered a barrier or non-speculative "
+                    "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
+                    head_inst->seqNum, head_inst->readPC());
+
+#if !FULL_SYSTEM
+            // Hack to make sure syscalls/memory barriers/quiesces
+            // aren't executed until all stores write back their data.
+            // This direct communication shouldn't be used for
+            // anything other than this.
+            if (inst_num > 0 || iewStage->hasStoresToWB())
+#else
+            if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
+                    head_inst->isQuiesce()) &&
+                iewStage->hasStoresToWB())
+#endif
+            {
+                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
+                return false;
+            }
 
-            toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
+            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
 
             // Change the instruction so it won't try to commit again until
             // it is executed.
@@ -372,74 +979,111 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
             ++commitNonSpecStalls;
 
             return false;
+        } else if (head_inst->isLoad()) {
+            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
+                    head_inst->seqNum, head_inst->readPC());
+
+            // Send back the non-speculative instruction's sequence
+            // number.  Tell the lsq to re-execute the load.
+            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
+            toIEW->commitInfo[tid].uncached = true;
+            toIEW->commitInfo[tid].uncachedLoad = head_inst;
+
+            head_inst->clearCanCommit();
+
+            return false;
         } else {
-            panic("Commit: Trying to commit un-executed instruction "
+            panic("Trying to commit un-executed instruction "
                   "of unknown type!\n");
         }
     }
 
-    // Now check if it's one of the special trap or barrier or
-    // serializing instructions.
-    if (head_inst->isThreadSync()  ||
-        head_inst->isSerializing() ||
-        head_inst->isMemBarrier()  ||
-        head_inst->isWriteBarrier() )
-    {
-        // Not handled for now.  Mem barriers and write barriers are safe
-        // to simply let commit as memory accesses only happen once they
-        // reach the head of commit.  Not sure about the other two.
-        panic("Serializing or barrier instructions"
-              " are not handled yet.\n");
+    if (head_inst->isThreadSync()) {
+        // Not handled for now.
+        panic("Thread sync instructions are not handled yet.\n");
+    }
+
+    // Stores mark themselves as completed.
+    if (!head_inst->isStore()) {
+        head_inst->setCompleted();
+    }
+
+    // Use checker prior to updating anything due to traps or PC
+    // based events.
+    if (cpu->checker) {
+        cpu->checker->tick(head_inst);
     }
 
     // Check if the instruction caused a fault.  If so, trap.
     Fault inst_fault = head_inst->getFault();
 
     if (inst_fault != NoFault) {
-        if (!head_inst->isNop()) {
+        head_inst->setCompleted();
 #if FULL_SYSTEM
-            cpu->trap(inst_fault);
-#else // !FULL_SYSTEM
-            panic("fault (%d) detected @ PC %08p", inst_fault,
-                  head_inst->PC);
-#endif // FULL_SYSTEM
+        DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
+                head_inst->seqNum, head_inst->readPC());
+
+        if (iewStage->hasStoresToWB() || inst_num > 0) {
+            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
+            return false;
         }
-    }
 
-    // Check if we're really ready to commit.  If not then return false.
-    // I'm pretty sure all instructions should be able to commit if they've
-    // reached this far.  For now leave this in as a check.
-    if (!rob->isHeadReady()) {
-        panic("Commit: Unable to commit head instruction!\n");
-        return false;
-    }
+        if (cpu->checker && head_inst->isStore()) {
+            cpu->checker->tick(head_inst);
+        }
 
-    // If it's a branch, then send back branch prediction update info
-    // to the fetch stage.
-    // This should be handled in the iew stage if a mispredict happens...
+        assert(!thread[tid]->inSyscall);
 
-    if (head_inst->isControl()) {
+        // Mark that we're in state update mode so that the trap's
+        // execution doesn't generate extra squashes.
+        thread[tid]->inSyscall = true;
 
-#if 0
-        toIEW->nextPC = head_inst->readPC();
-        //Maybe switch over to BTB incorrect.
-        toIEW->btbMissed = head_inst->btbMiss();
-        toIEW->target = head_inst->nextPC;
-        //Maybe also include global history information.
-        //This simple version will have no branch prediction however.
-#endif
+        // DTB will sometimes need the machine instruction for when
+        // faults happen.  So we will set it here, prior to the DTB
+        // possibly needing it for its fault.
+        thread[tid]->setInst(
+            static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
+
+        // Execute the trap.  Although it's slightly unrealistic in
+        // terms of timing (as it doesn't wait for the full timing of
+        // the trap event to complete before updating state), it's
+        // needed to update the state as soon as possible.  This
+        // prevents external agents from changing any specific state
+        // that the trap need.
+        cpu->trap(inst_fault, tid);
+
+        // Exit state update mode to avoid accidental updating.
+        thread[tid]->inSyscall = false;
+
+        commitStatus[tid] = TrapPending;
 
-        ++commitCommittedBranches;
+        // Generate trap squash event.
+        generateTrapEvent(tid);
+
+        return false;
+#else // !FULL_SYSTEM
+        panic("fault (%d) detected @ PC %08p", inst_fault,
+              head_inst->PC);
+#endif // FULL_SYSTEM
     }
 
-    // Now that the instruction is going to be committed, finalize its
-    // trace data.
+    updateComInstStats(head_inst);
+
     if (head_inst->traceData) {
+        head_inst->traceData->setFetchSeq(head_inst->seqNum);
+        head_inst->traceData->setCPSeq(thread[tid]->numInst);
         head_inst->traceData->finalize();
+        head_inst->traceData = NULL;
+    }
+
+    // Update the commit rename map
+    for (int i = 0; i < head_inst->numDestRegs(); i++) {
+        renameMap[tid]->setEntry(head_inst->destRegIdx(i),
+                                 head_inst->renamedDestRegIdx(i));
     }
 
-    //Finally clear the head ROB entry.
-    rob->retireHead();
+    // Finally clear the head ROB entry.
+    rob->retireHead(tid);
 
     // Return true to indicate that we have committed an instruction.
     return true;
@@ -447,37 +1091,39 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
 template <class Impl>
 void
-SimpleCommit<Impl>::getInsts()
+DefaultCommit<Impl>::getInsts()
 {
-    //////////////////////////////////////
-    // Handle ROB functions
-    //////////////////////////////////////
-
-    // Read any issued instructions and place them into the ROB.  Do this
-    // prior to squashing to avoid having instructions in the ROB that
-    // don't get squashed properly.
+    // Read any renamed instructions and place them into the ROB.
     int insts_to_process = min((int)renameWidth, fromRename->size);
 
-    for (int inst_num = 0;
-         inst_num < insts_to_process;
-         ++inst_num)
+    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
     {
-        if (!fromRename->insts[inst_num]->isSquashed()) {
-            DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
-                    fromRename->insts[inst_num]->readPC());
-            rob->insertInst(fromRename->insts[inst_num]);
+        DynInstPtr inst = fromRename->insts[inst_num];
+        int tid = inst->threadNumber;
+
+        if (!inst->isSquashed() &&
+            commitStatus[tid] != ROBSquashing) {
+            changedROBNumEntries[tid] = true;
+
+            DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
+                    inst->readPC(), inst->seqNum, tid);
+
+            rob->insertInst(inst);
+
+            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
+
+            youngestSeqNum[tid] = inst->seqNum;
         } else {
-            DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
+            DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                     "squashed, skipping.\n",
-                    fromRename->insts[inst_num]->seqNum,
-                    fromRename->insts[inst_num]->readPC());
+                    inst->readPC(), inst->seqNum, tid);
         }
     }
 }
 
 template <class Impl>
 void
-SimpleCommit<Impl>::markCompletedInsts()
+DefaultCommit<Impl>::markCompletedInsts()
 {
     // Grab completed insts out of the IEW instruction queue, and mark
     // instructions completed within the ROB.
@@ -485,18 +1131,177 @@ SimpleCommit<Impl>::markCompletedInsts()
          inst_num < fromIEW->size && fromIEW->insts[inst_num];
          ++inst_num)
     {
-        DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
-                fromIEW->insts[inst_num]->readPC(),
-                fromIEW->insts[inst_num]->seqNum);
+        if (!fromIEW->insts[inst_num]->isSquashed()) {
+            DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
+                    "within ROB.\n",
+                    fromIEW->insts[inst_num]->threadNumber,
+                    fromIEW->insts[inst_num]->readPC(),
+                    fromIEW->insts[inst_num]->seqNum);
+
+            // Mark the instruction as ready to commit.
+            fromIEW->insts[inst_num]->setCanCommit();
+        }
+    }
+}
+
+template <class Impl>
+bool
+DefaultCommit<Impl>::robDoneSquashing()
+{
+    list<unsigned>::iterator threads = (*activeThreads).begin();
 
-        // Mark the instruction as ready to commit.
-        fromIEW->insts[inst_num]->setCanCommit();
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (!rob->isDoneSquashing(tid))
+            return false;
     }
+
+    return true;
 }
 
 template <class Impl>
-uint64_t
-SimpleCommit<Impl>::readCommitPC()
+void
+DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
 {
-    return rob->readHeadPC();
+    unsigned thread = inst->threadNumber;
+
+    //
+    //  Pick off the software prefetches
+    //
+#ifdef TARGET_ALPHA
+    if (inst->isDataPrefetch()) {
+        statComSwp[thread]++;
+    } else {
+        statComInst[thread]++;
+    }
+#else
+    statComInst[thread]++;
+#endif
+
+    //
+    //  Control Instructions
+    //
+    if (inst->isControl())
+        statComBranches[thread]++;
+
+    //
+    //  Memory references
+    //
+    if (inst->isMemRef()) {
+        statComRefs[thread]++;
+
+        if (inst->isLoad()) {
+            statComLoads[thread]++;
+        }
+    }
+
+    if (inst->isMemBarrier()) {
+        statComMembars[thread]++;
+    }
+}
+
+////////////////////////////////////////
+//                                    //
+//  SMT COMMIT POLICY MAINTAINED HERE //
+//                                    //
+////////////////////////////////////////
+template <class Impl>
+int
+DefaultCommit<Impl>::getCommittingThread()
+{
+    if (numThreads > 1) {
+        switch (commitPolicy) {
+
+          case Aggressive:
+            //If Policy is Aggressive, commit will call
+            //this function multiple times per
+            //cycle
+            return oldestReady();
+
+          case RoundRobin:
+            return roundRobin();
+
+          case OldestReady:
+            return oldestReady();
+
+          default:
+            return -1;
+        }
+    } else {
+        int tid = (*activeThreads).front();
+
+        if (commitStatus[tid] == Running ||
+            commitStatus[tid] == Idle ||
+            commitStatus[tid] == FetchTrapPending) {
+            return tid;
+        } else {
+            return -1;
+        }
+    }
+}
+
+template<class Impl>
+int
+DefaultCommit<Impl>::roundRobin()
+{
+    list<unsigned>::iterator pri_iter = priority_list.begin();
+    list<unsigned>::iterator end      = priority_list.end();
+
+    while (pri_iter != end) {
+        unsigned tid = *pri_iter;
+
+        if (commitStatus[tid] == Running ||
+            commitStatus[tid] == Idle) {
+
+            if (rob->isHeadReady(tid)) {
+                priority_list.erase(pri_iter);
+                priority_list.push_back(tid);
+
+                return tid;
+            }
+        }
+
+        pri_iter++;
+    }
+
+    return -1;
+}
+
+template<class Impl>
+int
+DefaultCommit<Impl>::oldestReady()
+{
+    unsigned oldest = 0;
+    bool first = true;
+
+    list<unsigned>::iterator threads = (*activeThreads).begin();
+
+    while (threads != (*activeThreads).end()) {
+        unsigned tid = *threads++;
+
+        if (!rob->isEmpty(tid) &&
+            (commitStatus[tid] == Running ||
+             commitStatus[tid] == Idle ||
+             commitStatus[tid] == FetchTrapPending)) {
+
+            if (rob->isHeadReady(tid)) {
+
+                DynInstPtr head_inst = rob->readHeadInst(tid);
+
+                if (first) {
+                    oldest = tid;
+                    first = false;
+                } else if (head_inst->seqNum < oldest) {
+                    oldest = tid;
+                }
+            }
+        }
+    }
+
+    if (!first) {
+        return oldest;
+    } else {
+        return -1;
+    }
 }