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author | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2014-01-24 15:29:30 -0600 |
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committer | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2014-01-24 15:29:30 -0600 |
commit | 9633282fc8f152ba897347d38fa85a7b374e3d1e (patch) | |
tree | aa619c797ae5aad914639758c71b595cd71ac117 /src/cpu/o3/commit_impl.hh | |
parent | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (diff) | |
download | gem5-9633282fc8f152ba897347d38fa85a7b374e3d1e.tar.xz |
checker: CheckerCPU handling of MiscRegs was incorrect
The CheckerCPU model in pre-v8 code was not checking the
updates to miscellaneous registers due to some methods
for setting misc regs were not instrumented. The v8 patches
exposed this by calling the instrumented misc reg update
methods and then invoking the checker before the main CPU had
updated its misc regs, leading to false positives about
register mismatches. This patch fixes the non-instrumented
misc reg update methods and places calls to the checker in
the proper places in the O3 model.
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index a6f2a63db..91e8e7681 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1043,6 +1043,12 @@ DefaultCommit<Impl>::commitInsts() // Updates misc. registers. head_inst->updateMiscRegs(); + // Check instruction execution if it successfully commits and + // is not carrying a fault. + if (cpu->checker) { + cpu->checker->verify(head_inst); + } + cpu->traceFunctions(pc[tid].instAddr()); TheISA::advancePC(pc[tid], head_inst->staticInst); @@ -1168,12 +1174,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->setCompleted(); } - // Use checker prior to updating anything due to traps or PC - // based events. - if (cpu->checker) { - cpu->checker->verify(head_inst); - } - if (inst_fault != NoFault) { DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", head_inst->seqNum, head_inst->pcState()); @@ -1185,6 +1185,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->setCompleted(); + // If instruction has faulted, let the checker execute it and + // check if it sees the same fault and control flow. if (cpu->checker) { // Need to check the instruction before its fault is processed cpu->checker->verify(head_inst); |