Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.

src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94

1 files changed, 1 insertions, 1 deletions

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 6ae01ae67..c80e4d8c1 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1095,7 +1095,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 //            (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
 //        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
         thread[tid]->profilePC = head_inst->readPC();
-        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(),
+        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
                                                           head_inst->staticInst);
 
         if (node)