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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
commit | e681c0f7b30f521805ebec04271435306f4c56ed (patch) | |
tree | 4b060d7175b0d90c9d4a731d0cad304b60dac029 /src/cpu/o3/commit_impl.hh | |
parent | 719f9a6d4fba16af38dcfd62b25a4d708156699f (diff) | |
download | gem5-e681c0f7b30f521805ebec04271435306f4c56ed.tar.xz |
O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 1a44c64ee..2895de293 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -561,6 +561,33 @@ DefaultCommit<Impl>::squashFromTC(ThreadID tid) template <class Impl> void +DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) +{ + youngestSeqNum[tid] = squash_after_seq_num; + + rob->squash(squash_after_seq_num, tid); + changedROBNumEntries[tid] = true; + + // Send back the sequence number of the squashed instruction. + toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; + + // Send back the squash signal to tell stages that they should squash. + toIEW->commitInfo[tid].squash = true; + + // Send back the rob squashing signal so other stages know that + // the ROB is in the process of squashing. + toIEW->commitInfo[tid].robSquashing = true; + + toIEW->commitInfo[tid].branchMispredict = false; + + toIEW->commitInfo[tid].pc = pc[tid]; + DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", + tid, squash_after_seq_num); + commitStatus[tid] = ROBSquashing; +} + +template <class Impl> +void DefaultCommit<Impl>::tick() { wroteToTimeBuffer = false; @@ -917,6 +944,11 @@ DefaultCommit<Impl>::commitInsts() TheISA::advancePC(pc[tid], head_inst->staticInst); + // If this is an instruction that doesn't play nicely with + // others squash everything and restart fetch + if (head_inst->isSquashAfter()) + squashAfter(tid, head_inst->seqNum); + int count = 0; Addr oldpc; // Debug statement. Checks to make sure we're not |