diff options
| author | Kevin Lim <ktlim@umich.edu> | 2008-09-26 07:44:07 -0700 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2008-09-26 07:44:07 -0700 |
| commit | b7849032072ed7e93979d625cade3b384aa19948 (patch) | |
| tree | cf8f9578c9cc9b77cd99606875a366f1f303dad9 /src/cpu/o3/commit_impl.hh | |
| parent | 712a8ee70090abc8c8c0fdb4a907e3ec419ae56e (diff) | |
| download | gem5-b7849032072ed7e93979d625cade3b384aa19948.tar.xz | |
O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 86b4da8ce..b16955691 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -814,7 +814,7 @@ DefaultCommit<Impl>::commit() // @todo: Make this handle multi-cycle communication between // commit and IEW. if (checkEmptyROB[tid] && rob->isEmpty(tid) && - !iewStage->hasStoresToWB() && !committedStores[tid]) { + !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { checkEmptyROB[tid] = false; toIEW->commitInfo[tid].usedROB = true; toIEW->commitInfo[tid].emptyROB = true; @@ -968,7 +968,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", head_inst->seqNum, head_inst->readPC()); - if (inst_num > 0 || iewStage->hasStoresToWB()) { + if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { DPRINTF(Commit, "Waiting for all stores to writeback.\n"); return false; } @@ -983,7 +983,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) return false; } else if (head_inst->isLoad()) { - if (inst_num > 0 || iewStage->hasStoresToWB()) { + if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { DPRINTF(Commit, "Waiting for all stores to writeback.\n"); return false; } @@ -1038,7 +1038,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", head_inst->seqNum, head_inst->readPC()); - if (iewStage->hasStoresToWB() || inst_num > 0) { + if (iewStage->hasStoresToWB(tid) || inst_num > 0) { DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); return false; } |