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authorNikos Nikoleris <nikos.nikoleris@arm.com>2017-07-25 10:31:23 +0100
committerNikos Nikoleris <nikos.nikoleris@arm.com>2017-10-13 08:41:08 +0000
commitf6ff203ea591bf713a10d7cd0a22ee7ea936eab9 (patch)
tree7e96e5ea545786f7204bb6b10fc358c168504e9c /src/cpu/o3/commit_impl.hh
parente519aa4ac2942915355f0ef12e88286322336419 (diff)
downloadgem5-f6ff203ea591bf713a10d7cd0a22ee7ea936eab9.tar.xz
cpu-o3: Avoid early checker verification for store conditionals
The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3/commit_impl.hh')
-rw-r--r--src/cpu/o3/commit_impl.hh8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index bf5ee8a38..b3a97ad3a 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2014 ARM Limited
+ * Copyright (c) 2010-2014, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1044,6 +1044,12 @@ DefaultCommit<Impl>::commitInsts()
(!(pc[0].instAddr() & 0x3)));
}
+ // at this point store conditionals should either have
+ // been completed or predicated false
+ assert(!head_inst->isStoreConditional() ||
+ head_inst->isCompleted() ||
+ !head_inst->readPredicate());
+
// Updates misc. registers.
head_inst->updateMiscRegs();