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authorAli Saidi <Ali.Saidi@ARM.com>2011-12-01 00:15:22 -0800
committerAli Saidi <Ali.Saidi@ARM.com>2011-12-01 00:15:22 -0800
commit14441039988265b4cb64679fcae0ddb41f1f5e32 (patch)
tree977b1e89470d4f09ddf02e02188842e5e3b390c6 /src/cpu/o3/cpu.cc
parent93fb460faded99c640ff0d7273611932a9ebc46c (diff)
downloadgem5-14441039988265b4cb64679fcae0ddb41f1f5e32.tar.xz
O3: Add stat that counts how many cycles the O3 cpu was quiesced.
--HG-- extra : rebase_source : 043b9307eef3c5b87f8e6370765641e016ed1fa7
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 819495d62..94fc5cdf3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -442,6 +442,12 @@ FullO3CPU<Impl>::regStats()
"to idling")
.prereq(idleCycles);
+ quiesceCycles
+ .name(name() + ".quiesceCycles")
+ .desc("Total number of cycles that CPU has spent quiesced or waiting "
+ "for an interrupt")
+ .prereq(quiesceCycles);
+
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
@@ -688,6 +694,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
+ quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+
lastActivatedCycle = curTick();
_status = Running;
@@ -722,6 +730,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
+
+ DPRINTF(Quiesce, "Suspending Context\n");
+ lastRunningCycle = curTick();
_status = Idle;
}
@@ -1205,6 +1216,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
+
+ lastRunningCycle = curTick();
}
template <class Impl>