cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 75 insertions, 1 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 026907a94..d8f39bbe4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -170,7 +170,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
 
       regFile(params->numPhysIntRegs,
               params->numPhysFloatRegs,
-              params->numPhysCCRegs),
+              params->numPhysCCRegs,
+              params->numPhysVectorRegs),
 
       freeList(name() + ".freelist", &regFile),
 
@@ -269,6 +270,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
     assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
     assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
+    assert(params->numPhysVectorRegs >= numThreads * TheISA::NumVectorRegs);
 
     rename.setScoreboard(&scoreboard);
     iew.setScoreboard(&scoreboard);
@@ -313,6 +315,12 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
             renameMap[tid].setCCEntry(ridx, phys_reg);
             commitRenameMap[tid].setCCEntry(ridx, phys_reg);
         }
+
+        for (RegIndex ridx = 0; ridx < TheISA::NumVectorRegs; ++ridx) {
+            PhysRegIndex phys_reg = freeList.getVectorReg();
+            renameMap[tid].setVectorEntry(ridx, phys_reg);
+            commitRenameMap[tid].setVectorEntry(ridx, phys_reg);
+        }
     }
 
     rename.setRenameMap(renameMap);
@@ -521,6 +529,16 @@ FullO3CPU<Impl>::regStats()
         .desc("number of cc regfile writes")
         .prereq(ccRegfileWrites);
 
+    vectorRegfileReads
+        .name(name() + ".vector_regfile_reads")
+        .desc("number of vector regfile reads")
+        .prereq(vectorRegfileReads);
+
+    vectorRegfileWrites
+        .name(name() + ".vector_regfile_writes")
+        .desc("number of vector regfile writes")
+        .prereq(vectorRegfileWrites);
+
     miscRegfileReads
         .name(name() + ".misc_regfile_reads")
         .desc("number of misc regfile reads")
@@ -807,6 +825,18 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
         scoreboard.setReg(phys_reg);
     }
 
+    //Bind vector Regs to Rename Map
+    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs +
+              TheISA::NumVectorRegs;
+    for (int vreg = TheISA::NumIntRegs + TheISA::NumFloatRegs +
+                    TheISA::NumCCRegs;
+         vreg < max_reg; vreg++) {
+        PhysRegIndex phys_reg = freeList.getVectorReg();
+
+        renameMap[tid].setEntry(vreg, phys_reg);
+        scoreboard.setReg(phys_reg);
+    }
+
     //Copy Thread Data Into RegFile
     //this->copyFromTC(tid);
 
@@ -860,6 +890,14 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
         freeList.addReg(phys_reg);
     }
 
+    // Unbind condition-code Regs from Rename Map
+    max_reg = TheISA::Vector_Reg_Base + TheISA::NumVectorRegs;
+    for (int vreg = TheISA::Vector_Reg_Base; vreg < max_reg; vreg++) {
+        PhysRegIndex phys_reg = renameMap[tid].lookup(vreg);
+        scoreboard.unsetReg(phys_reg);
+        freeList.addReg(phys_reg);
+    }
+
     // Squash Throughout Pipeline
     DynInstPtr inst = commit.rob->readHeadInst(tid);
     InstSeqNum squash_seq_num = inst->seqNum;
@@ -1259,6 +1297,14 @@ FullO3CPU<Impl>::readCCReg(int reg_idx)
 }
 
 template <class Impl>
+const VectorReg &
+FullO3CPU<Impl>::readVectorReg(int reg_idx)
+{
+    vectorRegfileReads++;
+    return regFile.readVectorReg(reg_idx);
+}
+
+template <class Impl>
 void
 FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
@@ -1291,6 +1337,14 @@ FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
 }
 
 template <class Impl>
+void
+FullO3CPU<Impl>::setVectorReg(int reg_idx, const VectorReg &val)
+{
+    vectorRegfileWrites++;
+    regFile.setVectorReg(reg_idx, val);
+}
+
+template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 {
@@ -1331,6 +1385,16 @@ FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
 }
 
 template <class Impl>
+const VectorReg&
+FullO3CPU<Impl>::readArchVectorReg(int reg_idx, ThreadID tid)
+{
+    vectorRegfileReads++;
+    PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
+
+    return regFile.readVectorReg(phys_reg);
+}
+
+template <class Impl>
 void
 FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
 {
@@ -1371,6 +1435,16 @@ FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
 }
 
 template <class Impl>
+void
+FullO3CPU<Impl>::setArchVectorReg(int reg_idx, const VectorReg &val,
+                                  ThreadID tid)
+{
+    vectorRegfileWrites++;
+    PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
+    regFile.setVectorReg(phys_reg, val);
+}
+
+template <class Impl>
 TheISA::PCState
 FullO3CPU<Impl>::pcState(ThreadID tid)
 {