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authorAnouk Van Laer <anouk.vanlaer@arm.com>2017-03-17 12:02:00 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-11-20 11:03:03 +0000
commitc0d613adb4eca09c32aca1cc90f04c29574f69c6 (patch)
tree1c2a0d26778d8b8ca3f0b359f990dc695156bf8f /src/cpu/o3/cpu.cc
parentd626f4f7aaa4d2c9f7ae1afc35577fa025b4de38 (diff)
downloadgem5-c0d613adb4eca09c32aca1cc90f04c29574f69c6.tar.xz
pwr: Adds logic to enter power gating for the cpu model
If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 0695711f1..091c3a6ad 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1031,6 +1031,9 @@ template <class Impl>
DrainState
FullO3CPU<Impl>::drain()
{
+ // Deschedule any power gating event (if any)
+ deschedulePowerGatingEvent();
+
// If the CPU isn't doing anything, then return immediately.
if (switchedOut())
return DrainState::Drained;
@@ -1186,6 +1189,9 @@ FullO3CPU<Impl>::drainResume()
assert(!tickEvent.scheduled());
if (_status == Running)
schedule(tickEvent, nextCycle());
+
+ // Reschedule any power gating event (if any)
+ schedulePowerGatingEvent();
}
template <class Impl>